Array-based architecture for FET-based, nanoscale electronics

Abstract

Abstract-Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading.

Integrated logic synthesis using simulated annealing

“…The need for signal restoration limits the possible size of the basic logic block. The study of [169] shows that this can be helped by using nanoscale FET devices, which provide for both signal restoration and programming support for the switches. This opens a possibility for building macro-cells similar to PLAs using CAEN (for more information regarding PLAs, see Section 2.3).…”

“…This opens a possibility for building macro-cells similar to PLAs using CAEN (for more information regarding PLAs, see Section 2.3). Macrocells of 50-100 columns/rows are predicted to be feasible to be implemented in this manner [169].…”

Programmable Resistive-Switch Nanowire Transistor Logic Circuits

“…These efforts have provided data supporting the importance of crossbar array-based architectures, although cross-point differentiation, which is central to "programming" specific logic circuits, was predetermined by fabrication thus precluding the realization of a highly defect-tolerant and universal architecture. 3 Alternatively, hybrid structures consisting of simple twoterminal crossbar nanoswitch arrays with conventional CMOS transistor circuits, where the nanoswitch array is used for peripheral routing to form programmable architectures, have been studied. 10−13 While taking advantage of the power of conventional logic circuits, this approach does not address the long-standing goal 3 of building programmable circuits that could function as nanoprocessors from assembled nanowire or carbon nanotube semiconductor components.…”

“…[3][4][5]19,20 To this end, we recently introduced a dielectric charge-trapping shell structure on nanowire transistor elements and showed that by modulating the charge state in the dielectric layers the transistor could be programmed as "active" or "inactive" within a specific logic window. Integration of these nanowire device elements into a crossbar array 19,20 further yielded a basic module or tile that could be used for proposed array-based architecture.…”

“…Each crossbar array functions as a NOR logic gate unit, and in combination can yield complete logic functions dependent only on programming and the ultimate array sizes. 3,19,20 For our demonstration, we have considered a 2-to-4 demultiplexer with active resistive switch nodes indicated by green dots; an equivalent circuit is also shown for comparison (inset, Figure 4a We fabricated the 2-to-4 demultiplexer resistive-switch nanowire transistor crossbar circuit by assembling aligned Ge/Si nanowires using nanocombing 20,39 followed by conventional lithography. 34 Figure 4b (left panel) shows a SEM image of one of the fabricated arrays consisting of 10 nanowires with 6 device nodes on each nanowire.…”