ARM Virtualization: Performance and Architectural Implications

Dall, Christoffer; Li, Shih-Wei; Lim, Jin T. E.; Nieh, Jason; Koloventzos, Georgios

doi:10.1109/isca.2016.35

Cited by 29 publications

(16 citation statements)

References 11 publications

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“…Furthermore, the ARM architecture introduced a System Memory Management Unit (SMMU) and a 2-stage page translation process handling the translation and mapping of a virtual address (VA) to a physical address (PA) via a translation page table. In the first stage, the Virtual Address (VA) is mapped to an Intermediate Physical Address (IPA) which is controlled by the OS while at the second stage, the hypervisor performs the translation of the IPA to the Physical Address (PA) [5,17,12].…”

Section: A Arm Architecturementioning

confidence: 99%

“…Since ARM hardware-assisted virtualisation features do not support a VMCS memory structure, they do not automatically retain all guest and host processor states. Instead, ARM architectures enable the flexibility for software running on the EL2 exception level to decide which processor state it wants to save [12,10]. On the ARMv8 architecture, interrupts and exceptions have the same meaning and are used alternately.…”

Section: ) Migrating Cpu Statesmentioning

confidence: 99%

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Live migration on ARM-based micro-datacentres

Avramidis

Mackay

Tso

et al. 2018

2018 15th IEEE Annual Consumer Communications &Amp; Networking Conference (CCNC)

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Live migration, underpinned by virtualisation technologies, has enabled improved manageability and fault tolerance for servers. However, virtualised server infrastructures suffer from significant processing overheads, system inconsistencies, security issues and unpredictable performance which makes them unsuitable for low-power and resource-constraint computing devices that processing latency-sensitive, "Big-data"-type data. Consequently, we ask: "How do we eliminate the overhead of virtualisation whilst still retaining its benefits?" Motivated by this question, we investigate a practical approach for a bare-metal live migration scheme for ARM-based instances low-power servers and edge devices. In this paper, we position ARM-based bare-metal live migration as a technique that will underpin the efficiency on edge-computing and on Microdatacentres. We also introduce our early work on identifying three key technical challenges and discuss their solutions.

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Section: A Arm Architecturementioning

confidence: 99%

Section: ) Migrating Cpu Statesmentioning

confidence: 99%

Live migration on ARM-based micro-datacentres

Avramidis

Mackay

Tso

et al. 2018

2018 15th IEEE Annual Consumer Communications &Amp; Networking Conference (CCNC)

View full text Add to dashboard Cite

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“…Virtual Layered File Systems [144,145] introduced the core ideas of layers and repositories behind Docker and CoreOS. KVM/ARM [60] is widely deployed and used as the mainline Linux ARM hypervisor, and has led to improvements in ARM architectural support for virtualization [58]. MobiDesk [26], THINC [25], and other detailed measurement studies helped make the case for virtual desktop infrastructure, which has become widely used in industry.…”

Section: Authors' Perspectivesmentioning

confidence: 99%

“…ese hypervisors are useful to compare given their popularity and their different design choices. is work is based on a measurement study published in 2016 using state-of-the-art hardware for that time [58]. §8.1 first provides background regarding the current design of KVM and Xen.…”

Section: H a P T E Rmentioning

confidence: 99%

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Hardware and Software Support for Virtualization

Bugnion

Nieh

Tsafrir

2017

Synthesis Lectures on Computer Architecture

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A dual‐system trusted computing node construction method based on ARM multi‐core CPU architecture

Hong

Ning

Sun

et al. 2022

Concurrency and Computation

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Computer node security is the source and foundation of information system security. Trusted computing dual system architecture is an important implementation method to solve the security assurance by establishing the dual system of computing nodes, on the one hand, to achieve isolation on the other hand to achieve the active metrics of the system. This article systematically analyzes the dual architecture of trusted computing, summarizes the security assurance implementation of the dual architecture of trusted computing as the problem of trusted platform control module (TPCM) trusted root parallel access bus, and designs and implements it using ARM multi-core CPU architecture, and designs the basic hardware security assurance capabilities such as TPCM resource isolation, active metrics, secure communication and other key components of trusted cryptography module and trusted software base based on it, thus implementing the two core mechanisms of trustworthy computing, namely, trust chain construction and dynamic metrics, are implemented. The design of system integration in computing node devices based on this ARM multi-core CPU architecture is proposed, and the related design and implementation methods are proposed, and finally, the prototype implementation and test verification are performed on the Phytium CPU platform.

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ARM Virtualization: Performance and Architectural Implications

Cited by 29 publications

References 11 publications

Live migration on ARM-based micro-datacentres

Live migration on ARM-based micro-datacentres

Hardware and Software Support for Virtualization

A dual‐system trusted computing node construction method based on ARM multi‐core CPU architecture

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