2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) 2022
DOI: 10.1109/micro56248.2022.00086
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ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse

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Cited by 33 publications
(8 citation statements)
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“…However, F1 has a maximum polynomial degree support of only 16K, whereas RPU has no such limitations. More recent HE accelerators such as CraterLake [38], BTS [23], and ARK [22] target high multiplicative depth applications, but require large on-chip memories, e.g., 256MB for Craterlake. Craterlake supports up to 64K polynomial degree.…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…However, F1 has a maximum polynomial degree support of only 16K, whereas RPU has no such limitations. More recent HE accelerators such as CraterLake [38], BTS [23], and ARK [22] target high multiplicative depth applications, but require large on-chip memories, e.g., 256MB for Craterlake. Craterlake supports up to 64K polynomial degree.…”
Section: Related Workmentioning
confidence: 99%
“…Recent studies have focused on enhancing hybrid protocols through improved neural architecture design [5,6,13,20], protocol optimization [6,21,27,29], and hardware acceleration [18,22,23,36,38]. State-of-the-art PI protocols break the entire PI process into two phases, a pre-processing (or offline) phase and an online phase, to move expensive computations offline and improve online inference latency.…”
Section: Introductionmentioning
confidence: 99%
“…FHE accelerators for second-generation schemes have mostly been built after a classical CPU architecture [25,36,52]. They include a control unit that executes an instruction set, together with a set of arithmetic Processing Elements (PEs) that support different operations, e.g.…”
Section: Streaming Processormentioning
confidence: 99%
“…Of these dedicated implementations, GPU-based FHE accelerators are easiest to develop, but they typically only provide modest speedups [5,15,35,58]. At the other end of the spectrum, ASIC emulations in advanced technology nodes promise better FHE acceleration [25,36,37,52,53]. However, it can take years for these ASICs to be fabricated and become available [44], and they are typically specialized for a limited range of parameter sets.…”
Section: Introductionmentioning
confidence: 99%
“…To enhance FHE scheme performance, researchers have been exploring custom hardware accelerators using ASIC and FPGA technologies. ASIC solutions [ 10 , 11 , 12 , 13 ] show promise, as they surpass CPU/GPU implementations and bridge the performance gap between plaintext and ciphertext computations. However, to accommodate large on-chip memory, expensive advanced technology nodes such as 7 nm or 12 nm are required for ASIC implementations.…”
Section: Introductionmentioning
confidence: 99%