Arithmetic implementation techniques and methodologies for 3G uplink reception in Xilinx FPGAs

Macpherson, K.N.; Stirling, I.G.; Rice, G.W.; Garcia-Alis, D.; Stewart, Robert W.

doi:10.1049/cp:20020387

Cited by 11 publications

(7 citation statements)

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“…Figure 4 justifies that the RRC filter with roll-off factor 0.35 can withstand the peak ISI distortion of -41dB. Depending on the different applications several researches has been carried over on the various architecture of RRC filter implementation [29][30][31][32]. The increasing demand of the high speed with low computational complexity pulse shaping filter, in the signal processing field has become the key point of the research in RRC filter implementation.…”

Section: Pulse Shaping Filtermentioning

confidence: 99%

Multi-Standard Programmable Baseband Modulator for Next Generation Wireless Communication

Hatai¹,

Chakrabarti²

2010

IJCNC

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Section: Pulse Shaping Filtermentioning

confidence: 99%

Multi-Standard Programmable Baseband Modulator for Next Generation Wireless Communication

Hatai¹,

Chakrabarti²

2010

IJCNC

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“…The transpose structure with product generation hardware is the most efficient technique for FPGA implementation within the main logic fabric [3]. Advantages of the transpose are:…”

Section: Transpose Form Fir With Product Generation Hardwarementioning

confidence: 99%

Low cost, high speed parallel FIR digital filters for Software Radio on FPGAs

Macpherson¹,

Stirling²,

Stewart³

2003

IEE Colloquium on DSP Enabled Radio

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This paper discusses full-parallel FIR filters for FPGAs using their application in Digital DownConverters (DDCs) for Software Radio receivers as a background. A commercially available 4-channel, 40MHz DDC architecture implemented on a Xilinx Virtex-II FPGA is described as a basis and a 2-channel, 80MHz DDC system to be implemented on the same device is proposed. Various full-parallel filter structures are discussed and compared, leading to the transpose form FIR with multiplier graph/block being selected. This technique is described in detail along with example systems generated by the RSG HDL filter generation software and associated schematic viewer. Two implementations of the required low-pass decimation filters are generated and compared using RSG and the Xilinx Distributed Arithmetic core. The proposed 2-channel, 80MHz DDC is bit-true modelled in SystemView by Elanix, implemented in VHDL and verified via simulation. The proposed DDC using RSG filters is found to require less FPGA resource the original 4-channel, 40MHz DDC and the proposed DDC using Xilinx filters.

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“…The RC filters are required to avoid inter-symbol interference and constrain the amount of bandwidth required for transmission [6]. Raised Cosine (RC) is a favorable filter to do pulse shaping as it transition band is shaped like a cosine curve and the response meets the Nyquist Criteria [7].…”

Section: Introductionmentioning

confidence: 99%