Arithmetic compaction circuits for mixed-signal systems testing

Geurkov, Vadim; Kirischian, Lev

doi:10.1109/autest.2012.6334550

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2016

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“…Then, by selecting the degree one polynomial over GF(2 m ), g(y) = y + α (i.e. one stage signature analyzer), the compression process can be represented as [19]:…”

Section: Testing Conceptmentioning

confidence: 99%

Signature and Residue Testing of Microprogrammable Control Units

Geurkov

2016

IEEE Access

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Arithmetic and algebraic codes are used in testing to verify arithmetic and logical operations performed by digital circuits. An important unit of the hardware that implements arithmetic codes is a residue generator. This is a circuit that generates the residue of a number with respect to a check base. The existing design methods for residue generators are oriented to the special values of the check base. We propose an approach to designing the residue generators with an arbitrary check base. We show how to reduce the probability of error escape, when this type of generator is used for detecting arithmetic errors. We then demonstrate how to embed the designed circuit into a microprogrammable finite state machine to test its operation without adding test hardware overhead. The proposed scheme can be used in arithmetic/algebraic error-control coding and fault-tolerant digital designs.

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“…Then, by selecting the degree one polynomial over GF(2 m ), g(y) = y + α (i.e. one stage signature analyzer), the compression process can be represented as [19]:…”

Section: Testing Conceptmentioning

confidence: 99%

Signature and Residue Testing of Microprogrammable Control Units

Geurkov

2016

IEEE Access

Self Cite

View full text Add to dashboard Cite

show abstract

Arithmetic compaction circuits for mixed-signal systems testing

Cited by 1 publication

References 6 publications

Signature and Residue Testing of Microprogrammable Control Units

Signature and Residue Testing of Microprogrammable Control Units

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