Area-time efficient two's complement square rooting

Abstract

The conventional two's complement digit serial square root structure processes an n-bit digit every clock cycle. Therefore, it generates one bit of the N-bit square root every m cycles, where m N/n. Instead of generating Kbits every mKcycles, these bits can be generated in m K 1 cycles only by overlapping K steps of the conventional digit serial algorithm. The new two's complement structure is a tree representation of the conventional one and therefore, it can be considered as a high radix approach of the digit serial structure. It will be shown that the proposed architecture is faster and might be cheaper than the conventional digit serial one. Moreover, it is the ® rst digit serial square root structure which is cheaper and faster than the two's complement binary bit parallel one.