2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020
DOI: 10.1109/isvlsi49217.2020.00071
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Area-Efficient Pipelined VLSI Architecture for Polar Decoder

Weihang Tan
1
,
Antian Wang
2
,
Yunhao Xu
3
et al.
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