Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

Duong-Ngoc, Phap; Kwon, Sunmin; Yoo, Dong-Hoon; Lee, Hanho

doi:10.1109/tcsi.2022.3225208

Cited by 15 publications

(9 citation statements)

References 41 publications

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“…Utilizing FFT for polynomial multiplication has become prevalent in security applications, including homomorphic encryption [35], [36] and post-quantum cryptography [37], [38]. These works target the multiplication of polynomials over the ring of integers, in which the FFT becomes an NTT.…”

Section: B Fft Acceleratorsmentioning

confidence: 99%

Number Systems for Deep Neural Network Architectures

Alsuhli,

Sakellariou,

Saleh

et al. 2024

Synthesis Lectures on Engineering, Science, and Technology

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Quantum computing is an emerging technology on the verge of reshaping industries, while simultaneously challenging existing cryptographic algorithms. FALCON, a recent standard quantum-resistant digital signature, presents a challenging hardware implementation due to its extensive non-integer polynomial operations, necessitating FFT over the ring Q[x]/(x n +1). This paper introduces an ultra-low power and compact processor tailored for FFT/IFFT operations over the ring, specifically optimized for FALCON applications on resource-constrained edge devices. The proposed processor incorporates various optimization techniques, including twiddle factor compression and conflict-free scheduling. In an ASIC implementation using a 22 nm GF process, the proposed processor demonstrates an area occupancy of 0.15 mm 2 and a power consumption of 12.6 mW at an operating frequency of 167 MHz. Since a hardware implementation of FFT/IFFT over the ring is currently non-existent, the execution time achieved by this processor is compared to the software implementation of FFT/IFFT of FALCON on a Raspberry Pi 4 with Cortex-A72, where the proposed processor achieves a speedup of up to 2.3×. Furthermore, in comparison to dedicated state-of-the-art hardware accelerators for classic FFT, this processor occupies 42% less area and consumes 83% less power, on average. This suggests that the proposed hardware design offers a promising solution for implementing FALCON on resource-constrained devices.

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Section: B Fft Acceleratorsmentioning

confidence: 99%

Number Systems for Deep Neural Network Architectures

Alsuhli,

Sakellariou,

Saleh

et al. 2024

Synthesis Lectures on Engineering, Science, and Technology

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“…Conventionally, the NTT and INTT units consume a large amount of internal memory to store precomputed TFs. In this study, the proposed KeySwitch module employs in-place NTT and INTT hardware designs that aim to reduce the on-chip memory usage [ 20 ]. In particular, each NTT and INTT unit stores several TF bases of the associated modulus and utilizes built-in twiddle factor generator (TFG) to twiddle all other factors.…”

Section: Keyswitch Hardware Architecturementioning

confidence: 99%

“…In particular, each NTT and INTT unit stores several TF bases of the associated modulus and utilizes built-in twiddle factor generator (TFG) to twiddle all other factors. Based on the design method of [ 20 ] and the exploration of the key switching execution, we designed different NTT modules for associated moduli through pipeline stages. By adopting this approach, the proposed KeySwitch module utilizes hardware resources more efficiently.…”

Section: Keyswitch Hardware Architecturementioning

confidence: 99%

“…This study presents a comprehensive hardware architecture for the KeySwitch accelerator design, which operates in a highly pipelined manner to speed up CKKS-based FHE schemes. Built on compact NTT and INTT engines [ 20 ], the KeySwitch module efficiently employs on-chip resources. Importantly, our design approach significantly reduces internal memory consumption, allowing on-chip memory to hold temporary data.…”

Section: Introductionmentioning

confidence: 99%

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Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Duong-Ngoc

Lee

2023

Sensors

Self Cite

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The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.

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“…To address these performance bottlenecks, there exist works that focus on accelerating sub-operations like NTT [16]- [26] in en/decryption and pseudo-random number generation (PRNG) [16]- [18] in error sampling. For accelerating the complete encryption and decryption operations, Su et al [27] and Yoon et al [28] proposed an FPGA-based and an ASIC-based accelerator, respectively, targeting Brakerski-Gentry-Vaikuntanathan (BGV) HE scheme [29].…”

Section: Introductionmentioning

confidence: 99%

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Azad¹,

Yang²,

Agrawal³

et al. 2023

Preprint

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Today edge devices commonly connect to the cloud to use its storage and compute capabilities. This leads to security and privacy concerns about user data. Homomorphic Encryption (HE) is a promising solution to address the data privacy problem as it allows arbitrarily complex computations on encrypted data without ever needing to decrypt it. While there has been a lot of work on accelerating HE computations in the cloud, little attention has been paid to the message-to-ciphertext and ciphertext-to-message conversion operations on the edge. In this work, we profile the edge-side conversion operations, and our analysis shows that during conversion error sampling, encryption, and decryption operations are the bottlenecks. To overcome these bottlenecks, we present RISE, an area and energy-efficient RISC-V SoC. RISE leverages an efficient and lightweight pseudorandom number generator core and combines it with fast sampling techniques to accelerate the error sampling operations. To accelerate the encryption and decryption operations, RISE uses scalable, data-level parallelism to implement the number theoretic transform operation, the main bottleneck within the encryption and decryption operations. In addition, RISE saves area by implementing a unified en/decryption datapath, and efficiently exploits techniques like memory reuse and data reordering to utilize a minimal amount of on-chip memory. We evaluate RISE using a complete RTL design containing a RISC-V processor interfaced with our accelerator. Our analysis reveals that for message-to-ciphertext conversion and ciphertextto-message conversion, using RISE leads up to 6191.19× and 2481.44× more energy-efficient solution, respectively, than when using just the RISC-V processor.

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Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

Cited by 15 publications

References 41 publications

Number Systems for Deep Neural Network Architectures

Number Systems for Deep Neural Network Architectures

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

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