Area-efficient nonrestoring radix- division

Bashagha, A. E.

doi:10.1016/j.dsp.2005.01.003

Cited by 2 publications

(18 citation statements)

References 9 publications

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“…The original nonrestoring algorithm [14] like the classical high radix restoring one [13] requires full wordlength additions and therefore, the carry-out bits, c N+k+1 …”

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

“…The original nonrestoring algorithm [14] requires a set of 2 k−1 full wordlength additions/subtractions. In this section, a new radix-2 k nonrestoring division algorithm which makes use only of the (k + 2)-bit additions/subtractions will be presented.…”

Section: The Proposed Algorithmmentioning

confidence: 99%

“…1 [14]. Let the set of possible values of (6) be divided into two subsets, one for the positive values, {PR o i1 }, and the other for the negative values,…”

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

“…For instance if the minimum positive value is 2 k PR i−1 − 5D then Q i is equal to 101. In nonrestoring radix-2 k algorithm [14], only half of the values of the quotient digit set {Q} are used. These values could be the odd values or the even values.…”

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

“…As a result, a huge silicon area is required to implement the classical high radix restoring algorithm. Nonrestoring area-efficient radix-2 k algorithm that allows both addition and subtraction and uses only half of the multiples of the divisor has been proposed [14]. As a result, there will be a significant reduction in area.…”

Section: Introductionmentioning

confidence: 98%

See 4 more Smart Citations

High-performance two's complement divider

Bashagha

2007

AEU - International Journal of Electronics and Communications

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“…The original nonrestoring algorithm [14] like the classical high radix restoring one [13] requires full wordlength additions and therefore, the carry-out bits, c N+k+1 …”

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

Section: The Proposed Algorithmmentioning

confidence: 99%

“…1 [14]. Let the set of possible values of (6) be divided into two subsets, one for the positive values, {PR o i1 }, and the other for the negative values,…”

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

Section: Radix-2 K Nonrestoring Divisionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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High-performance two's complement divider

Bashagha

2007

AEU - International Journal of Electronics and Communications

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An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Guo

Cui

et al. 2015

J CIRCUIT SYST COMP

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In this paper, we propose a uni¯ed architecture for computation of double-precision°oatingpoint division, reciprocal, square root, inverse square root and multiplication with a signi¯cant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modi¯ed Goldschmidt algorithm to achieve better area e±ciency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the¯nal accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a recon¯gurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is¯nally implemented and synthesized in SMIC 0.13-m CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area e±ciency (performance/area ratio) of the proposed uni¯ed architecture is increased by about 20% in average, which is a better performance-area trade-o® for embedded microprocessors.

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Area-efficient nonrestoring radix- division

Cited by 2 publications

References 9 publications

High-performance two's complement divider

High-performance two's complement divider

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

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