Area-efficient multipliers for digital signal processing applications

Kidambi, S.S.; El-Guibaly, F.; Antoniou, A.

doi:10.1109/82.486455

Cited by 141 publications

(67 citation statements)

References 6 publications

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“…Applications Such as DSP, image processing and multimedia require extensive use of multiplication and squaring functions (Sheu and Lin, 2002;Walters et al, 2003). In many DSP processing algorithms such as digital filters, Discrete Cosine Transform (DCT) and wavelet transform, it is desirable to provide full precision multiplication and fixed width multiplication (Lim, 1992;Schulte and Swartzlander, 1993;Kidambi et al, 1996;Swartzlander, 1999;Van et al, 2000;Van and Yang, 2005) that produces n-bit output product with n-bit multiplier and n-bit multiplicand with low error. If the product is truncated to n-bits, the least-significant columns of the product matrix contribute little to the final result.…”

Section: Introductionmentioning

confidence: 99%

Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Rais¹

2010

American Journal of Engineering and Applied Sciences

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Problem statement: As growing demands on portable computing and communication systems, the power-efficient multipliers play an important role. In these multipliers basic multiplication follows the Baugh-Wooley algorithms and can easily be implemented using Field Programmable Gate Array (FPGA) devices because the development cost for Application Specific Integrated Circuits (ASICs) are high. These algorithms should be verified and optimized before implementation. Approach: This study presented the design and implementation of basic building blocks used in power-efficient Baugh-Wooley multipliers using FPGA Spartan-3AN device. The implementation of power-efficient Baugh-Wooley multipliers is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The design and implementation of basic building blocks of power-efficient Baugh-Wooley multipliers showed reasonable FPGA resource utilization, which is an indication that rest of the available resources could be utilized for other embedded resources. Conclusion: The Spartan-3AN FPGA device could be used at this stage of basic building blocks reasonably.

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Section: Introductionmentioning

confidence: 99%

Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Rais¹

2010

American Journal of Engineering and Applied Sciences

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“…In order to reduce the truncation error, many error compensation methods for fixed-width multipliers have been proposed in [4,5,6,7]. Error compensation biases of these methods can be classified into constant biases [4] and adaptive biases (or, data dependant biases) [5,6,7]. A constant bias is generated independent of the truncated partial products bits and is fixed for a given input word size.…”

Section: Introductionmentioning

confidence: 99%

Efficient unsigned squarer design techniques

Cho

2012

IEICE Electron. Express

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Abstract:The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an efficient unsigned parallel squarer design technique. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 18% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, area, propagation delay and power consumption can be further reduced up to 26%, 15% and 25%, respectively. Keywords: squarer, fixed-width, partial product reduction Classification: Integrated circuits References[1] J. Pihl and E. Aas, "A multiplier and squarer generator for high performance DSP applications,"

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“…Tables 1, 2 and 3 show simulated results for various fixed-width multipliers at different width s . The comparison results show that our proposed fixed-width multipliers are more accurate than others [2][3][4][5][6][7] for different values of w . The better performance is achieved due to the fact that we derive better error-compensation biases to reduce truncation error.…”

Section: Performance Discussionmentioning

confidence: 84%

“…The better performance is achieved due to the fact that we derive better error-compensation biases to reduce truncation error. The area-ratio in Table 4 shows that the proposed multiplier has nearly the same area-ratio as that of [4][5][6][7] at each value of w so that the lower-error fixed-width multiplier is area-efficient. Next, we apply the proposed fixed-width multiplier to the 35-tap FIR filter for speech processing.…”

Section: Performance Discussionmentioning

confidence: 98%

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A generalized methodology for lower-error area-efficient fixed-width multipliers

Van

Lee

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two's-complement multipliers that receive two s -bit numbers and produce an s -bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width multipliers suitable for VLSI realization.

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Area-efficient multipliers for digital signal processing applications

Cited by 141 publications

References 6 publications

Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Efficient unsigned squarer design techniques

A generalized methodology for lower-error area-efficient fixed-width multipliers

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