Area efficient layout design of CMOS circuit for high-density ICs

Mishra, Vimal Kumar; Chauhan, R. K.

doi:10.1080/00207217.2017.1340978

Cited by 9 publications

(3 citation statements)

References 15 publications

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“…This results in switching ratio greater than 10 11 , which is much higher as discussed in literatures. 25,35,36 This leads to a motivation to further analyze the studied high-k dielectric-based nanoscaled MOSFET for the design of highly linear RF subsystems. Next, the analysis of linearity performance and intermodulation distortion itself explains that the device is suitable for high-frequency investigations.…”

Section: Discussionmentioning

confidence: 99%

“…This signifies that the immunity of device-D 2 over SCEs is excellent as compared to other available literatures. 12,15,25,35,36 This is due to the introduced DMIG technique in the design of FD SOI MOSFET. As, the DMIG technique will offer step-like potential profile which will further increase the average electric field under the first metal gate (M1).…”

Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

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Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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Fully-Depleted Silicon-on-Insulator (FD SOI) MOS technology has already been reported as a strong contender in nanoscale CMOS designs. This work presents the linearity-distortion assessment, small-signal and radio-frequency noise-behavior of dual-metal-insulated-gate (DMIG) source-engineered (SE) FD SOI MOSFET for terahertz (THz) applications. Here, linearity-distortion performance has been monitored on the basis of numerical calculations of transconductance and its higher-order derivatives along with the voltage-intercept points, and various parameters of intermodulation-distortion. This analysis also practices the guidelines of device design with least linearity-distortion in radio-frequency integrated-circuits based communication systems at 50 nm technology node. Further, the small-signal and RF noise-behavior have been examined on the basis of high-frequency scattering-parameters for the analysis of input/output reflection-coefficients (S11/S22), reverse/forward transmission-coefficients (S12/S21), Stern's-stability-factor (K), minimum noise-figure, noise-conductance and cross-correlation factor (). The analysed results affirm the ultimate reduction in reflection-coefficients and a significant increase in transmission-coefficients in case of DMIG FD SOI MOSFET at THz range as compared to existing MOS structures. Also, the analysis reveals the considerable reduction in various radio-frequency noise FOMs and thus represents the device efficacy in low-noise-amplifiers. All these studies have been carried out by performing numerical simulations over TCAD-ATLAS simulator from Silvaco along with quantum-mechanical-effect (QME) and Bohm-quantum-potential (BQP) models.

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Section: Discussionmentioning

confidence: 99%

Section: Model Calibration and Short-channel Electrical Characteristi...mentioning

confidence: 99%

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Srivastava

Mishra

2019

ECS J. Solid State Sci. Technol.

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“…It should be noted that complex gates have been proposed as a valuable alternative in terms of area and delay [4]. From a transistor-layer point of view, multiple design frameworks were proposed in order to achieve area efficient layouts of radiation hardened devices [5], or highly dense integrated circuits (ICs) [6].…”

Section: Related Workmentioning

confidence: 99%

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

et al. 2018

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In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

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Performance Analysis of Hetero-Dielectric Stacked Buried Oxide on Modified Source-Drain FDSOI MOS Transistor

Rai

Chauhan

2022

Lecture Notes in Electrical Engineering

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Area efficient layout design of CMOS circuit for high-density ICs

Cited by 9 publications

References 15 publications

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Linearity Distortion Assessment and Small-Signal Behavior of Nano-Scaled SOI MOSFET for Terahertz Applications

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Performance Analysis of Hetero-Dielectric Stacked Buried Oxide on Modified Source-Drain FDSOI MOS Transistor

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