Area efficient FIR filters for high speed FPGA implementation

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

“…The effectiveness of the PMCM lower bound is demonstrated by examples, where pipelined shift-and-add multiple constant multiplication blocks are constructed using the algorithms from [7,8,22,30] and [36] for the case of 2-input additions and the algorithm from [10] for the case of 3-input additions. The proposed lower bound is compared with the lower bound from [3] in the case of 2-input additions, and in most of the cases, it provides better estimation of the number of required Roperations.…”

“…Example 3 presents the group of constants {3; 13; 21; 37} that form a multiplier block. The R-operations needed to implement the multiplier block using 2-input additions are obtained with the algorithms RAG-n [36] with pipelining, RSG [22], and OFL [7]. The resulting values are shown in Table 5, where it can be observed that the OFL algorithm offers the less number of R-operations.…”

“…Nevertheless, the critical path has the main negative impact in the speed and power consumption [13][14][15][16][17][18]. Therefore, substantial research activity has been carried out currently targeting both, application-specific integrated circuits (ASICs) [19][20][21] and FPGAs [5][6][7][8][9][10][22][23][24][25], where the minimization of the number of arithmetic operations subject to a minimum number of depth levels is the ultimate goal.…”

Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

“…Methods specifically aimed at FPGA based FIR filter implementations include the fully pipelined and full-parallel transposed form [20], Add-and-Shift method with advanced calculation [21], and hardware efficient distributed arithmetic for higher orders [12,13]. In [18], a new design technique based on a linear phase prototype filter that exploits coefficient symmetry was shown to offer better performance at a hardware cost similar to that of linear phase filters.…”

“…Apart from the classical multiplier complexity reduction techniques, a new approach called Slice Reduction Graphs (SRG) [20], which reduces area by minimizing the multiplier block logic depth and pipeline registers, has been shown to offer improved area-performance over the Reduced Adder Graph (RAG) and Distributed Arithmetic (DA) techniques. In [20], simulations were carried out at coefficient bit widths in the range of 2-20 bits, while keeping the order of the filter constant (i.e., at 51).…”