Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors

Paek, Seung-Kil; Oh, Jiehwan; Chung, Sang-Hye; Kim, Lee-Sup

doi:10.1109/iscas.2011.5937900

Cited by 3 publications

(3 citation statements)

References 14 publications

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“…This result is mainly due to the outstanding power consumption of the multiplying DLL and the PLL architecture in [18]. However, the DLL with frequency multiplier architecture has more chance to contribute to low power SoC design than the multiplying DLL and the PLL, because the DLL core can be shared with other essential building block in SoC such as a temperature sensor [19], [20].…”

Section: Measurement Resultsmentioning

confidence: 99%

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive-and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 µW/MHz. Index Terms-Clock generator, delay-locked loop (DLL), edge combiner, frequency multiplier.

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Section: Measurement Resultsmentioning

confidence: 99%

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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“…CMOS time-domain temperature sensors have advantages in the aspect of system integration and power consumption when considering digital code conversion blocks together, which should be taken into account because the final user of temperature information is digital logic blocks. The area reduction by sharing with clocking systems can also be expected [6]. However, the intrinsic nonlinearity of CMOS inverters, as in Fig.…”

Section: Introductionmentioning

confidence: 94%

“…The DLL also provides multi-phases for digital code converting. Using DLL has the advantage of area reduction because it can be shared by DLLs which are already equipped in many digital systems [6].…”

Section: Temperature-to-digital Covertermentioning

confidence: 99%

An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO)

Shin

Paek

Kim

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper describes CMOS time-domain temperature sensors. A principle of this type of sensors is CMOS inverter's time-delay variation with temperature. The variation, however, has nonlinearity which is a fundamental error source. Therefore, we propose a new temperature sensor that improves linearity using an injection-locked oscillator (ILO). Since the ILO has the opposite curvature of an inverter delay line in temperature domain, nonlinear error induced by the CMOS inverters can be eliminated. Integral nonlinearity (INL) error is reduced from 3.6 LSB to 0.56 LSB (84% reduction), resulting in under 1-bit error by nonlinearity. The proposed design has-0.19℃~0.2℃ inaccuracy which is only quantization error over 0℃~100℃. The power consumption is 2.88mW including an 8-bit temperatureto-digital code conversion block at the sampling rate of 15.6M samples/s. I.

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Temperature-aware thread assignment of many-core processor

Xuan

Yang²

2015

Sixteenth International Symposium on Quality Electronic Design

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Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors

Cited by 3 publications

References 14 publications

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO)

Temperature-aware thread assignment of many-core processor

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