Area efficient and high throughput CABAC encoder architecture for HEVC

Vizzotto, Bruno Boessio; Mazui, Volnei; Bampi, Sérgio

doi:10.1109/icecs.2015.7440381

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…Our proposed method in residual SE generation design is for power saving purposes via reducing memory access load. Its throughput of 3.5 SEs/cycle at 500 MHz is comparable with the results of [6,8,12]. The efficiency of our proposal in terms of throughput is a half of [7] as they proposed four parallel residual SE generation cores working at the operating frequency of 668 MHz.…”

Section: Residual Se Generation and Binarizersupporting

confidence: 76%

“…Its throughput is only 200 Mbins/s while our design's throughput is 1525 Mbins/s (7.6 times higher). Therefore, between the high-throughput designs [6][7][8]12], our proposal is the best (having a throughput-overhead efficiency of 1.293 Mbins/KGate/mW), 4× better than the work in [6] and 20× better than the work in [7]. In addition, if consider the power-efficiency (calculated by the throughput-power consumption ratio), our proposal is the most efficient design even compared with the work in [14].…”

Section: Se Gen + Bin Corementioning

confidence: 91%

“…Thus, it becomes the candidate Electronics 2020, 9, 684 6 of 12 for numerous researches that focus on designing efficient binarizer hardware architectures while maintaining the throughput requirement of the whole CABAC encoder. Vizzotto et al [12] proposed an area efficient and high throughput CABAC encoder, where almost CABAC components are optimized to support throughput improvement. In addition, a heterogeneous binarization core is proposed to support UHD applications while reducing area cost of up to 10 Kgates in comparison with traditional parallel binarization architecture.…”

Section: State-of-the-artmentioning

confidence: 99%

“…In fact, this issue has been focused recently to propose a higher performance binarizer. Vizzotto et al [12] proposed a heterogeneous binarization architecture for throughput improvement and area saving. Neji et al [13] presented a binarizer architecture for CABAC addressing hardware complexity, regularity, and modularity.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder

Tran

Bui

et al. 2020

Electronics

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HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.

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Section: Residual Se Generation and Binarizersupporting

confidence: 76%