Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

Thiruveni, M.; Shanthi, D.

doi:10.5573/jsts.2016.16.4.497

JSTS:Journal of Semiconductor Technology and Science

2016

DOI: 10.5573/jsts.2016.16.4.497

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Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

M. Thiruveni¹,

D. Shanthi²

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Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

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References 10 publications

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