Area and Power Efficient Pipeline FFT Architecture for QPSK-OFDM

Abstract

This paper proposes four-parallel pipelined fast Fourier transform (FFT) architecture for the discrete Fourier transform (DFT) computation of quadrature-phase-shiftkeying Orthogonal Frequency Division Multiplexing (QPSK-OFDM) signals. The first stage of the architecture is optimized with the multiplexer blocks that contain output values of QPSK as inputs. Furthermore, the proposed architecture employs a complex constant multipliers (CCMs) using adders and shifters that can reduce the total hardware of the design. The proposed 64-point pipeline architecture is modeled and implemented using UMC 65 nm CMOS technology with a supply voltage of 1.2 V. The results demonstrate that the proposed FFT architecture significantly reduces the hardware cost and power consumption in comparison to the recent FFT architecture.

An Analysis on the Conventional Partitioning Schemes of Partial Transmit Sequence in OFDM Systems

“…In the OFDM, The input data sequence X k = {k = 0, 1, 2, …, N-1} is mapped by one of the modulation techniques such as phase shifting keying (PSK), and quadrate amplitude modulation (QAM), where N denotes the number of the subcarriers. The baseband signal is converted from the serial into parallel and then performing IFFT to modulate the baseband signal with N subcarriers orthogonally [19]. The discrete baseband signal x(n) in the time-domain can be written as…”