Area and performance evaluation of central DMA controller in Xilinx embedded FPGA designs

Design, implementation, and test of an SDR for NVIS communications

“…A phase locked loop (PLL) is used to synchronize all the different parts of the hardware design, while implementing the local oscillator for the up and down conversion of the radiofrequency signal. As the operating system (OS) and hardware (FPGA) share the same peripherals (DDR RAM), an agile reconfiguration of the transceiver can be carried out. In particular, the center frequency, the transmission power, and the power range of the received signal are the most critical parameters that are changed dynamically.…”

“…The lower part named SO is the processing system (PS), which includes the operating system, the configuration files, and the management of peripherals. The two entities share access to the RAM memory through the direct memory access (DMA) device. The DMA is also in charge of the communication among the layers that exchange the data between the ADC and DAC converters.…”