2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID) 2020
DOI: 10.1109/vlsid49098.2020.00033
|View full text |Cite
|
Sign up to set email alerts
|

Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
4
2

Relationship

0
6

Authors

Journals

citations
Cited by 8 publications
(3 citation statements)
references
References 14 publications
0
3
0
Order By: Relevance
“…The maximum relative error of this approximation is found to be 0.0607 and the approximated value is always larger than the exact square root value 48 . This relative error can be reduced to 0.03476 by replacing the quantity 127 × 2 22 = 532, 676, 608 in Eq. ( 12), by a smaller value that is equal to 532,369,100 48 .…”
Section: Methods By Dianov Et Almentioning
confidence: 99%
“…The maximum relative error of this approximation is found to be 0.0607 and the approximated value is always larger than the exact square root value 48 . This relative error can be reduced to 0.03476 by replacing the quantity 127 × 2 22 = 532, 676, 608 in Eq. ( 12), by a smaller value that is equal to 532,369,100 48 .…”
Section: Methods By Dianov Et Almentioning
confidence: 99%
“…In the recent 2020 survey of approximate arithmetic circuits by Jiang et al [3], there are only two references for square root circuits, and of those, only one [4] is for an approximate square root. However, another recent work by Arya et al [5] proposes an alternative approximate square root design, and the approximate subtractor cells proposed by Chen et al [6,7] can be appropriated for use in an approximate square root design. The approximate square root circuit proposed by Jiang et al [4] is based on removing the most significant bits of the radicand A down to the first nonzero bit, truncating the least significant bits of A so that 2k bits remain, with k used as an approximation degree parameter, and then using an exact circuit for the remaining 2k bits.…”
Section: Related Workmentioning
confidence: 99%
“…Recently, Arya et al have proposed alternative approximate square root circuits [5] based on square root arrays with cells designed for area reduction and least significant bit truncation. These are simple designs in which the approximation cell used is simple wire fall-through connections for the horizontal and vertical input wires in the square root array of Figure 1.…”
Section: Related Workmentioning
confidence: 99%