Analog Circuit Design
DOI: 10.1007/1-4020-5186-7_2
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ARCHITECTURES AND ISSUES FOR GIGASAMPLE/SECOND ADCs

Abstract: Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8-bit ADCs operatin… Show more

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Cited by 3 publications
(5 citation statements)
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“…Even though CMOS scaling has made digital circuits highly power efficient, large amount of digital data is generated, which requires significant power consumption in digital post-processing. Digital power is estimated to be the same as the total power consumed in backend electronic ADCs (as a similar trend is observed in [13]). Using these numbers with 1-mW input optical power at each photo-detector, the total optical and electrical powers can be calculated.…”
Section: Power Calculations For a Time-stretch Adcsupporting
confidence: 54%
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“…Even though CMOS scaling has made digital circuits highly power efficient, large amount of digital data is generated, which requires significant power consumption in digital post-processing. Digital power is estimated to be the same as the total power consumed in backend electronic ADCs (as a similar trend is observed in [13]). Using these numbers with 1-mW input optical power at each photo-detector, the total optical and electrical powers can be calculated.…”
Section: Power Calculations For a Time-stretch Adcsupporting
confidence: 54%
“…However, from the trend seen in Fig. 1 and in [13], and from the discussion in the following subsection, it becomes clear that in reality, the energy per conversion step scales roughly as f s , i.e., power dissipation is proportional to f 2 s in high-speed ADCs.…”
Section: Fundamental Limits To Power Dissipation In Adcsmentioning
confidence: 92%
“…* The k-th sub-converter has intrinsic gain and sampling time error of (G k, zlt k), which is unknown. (2) Note that zk[n]'s and yk[n]'s are both observable and carry the same information since Gk's are known to the algorithm.…”
Section: System Configurationmentioning
confidence: 99%
“…One of the sensible choices of equalization reference is the following average autocorrelations, (2). For convenience, we ignore common time delay and assume the following in further discussions.…”
Section: A Selection Ofequalization Referencementioning
confidence: 99%
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