Architecture synthesis of high-performance application-specific processors

Breternitz, Maurício; Shen,

doi:10.1109/dac.1990.114915

Cited by 20 publications

(17 citation statements)

References 11 publications

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“…Early works on architectural synthesis for ASIPs are contained in [10] and [11]. An approach that generates new logic capabilities for a processor dynamically has been developed for an adaptive machine architecture in [12].…”

Section: A Related Workmentioning

confidence: 99%

Custom-Instruction Synthesis for Extensible-Processor Platforms

Sun

Ravi²,

Raghunathan³

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions. In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Furthermore, we employ a two-stage process, wherein a limited number of promising instruction candidates are first short-listed using efficient selection criteria, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint. We have evaluated the proposed techniques using a state-of-the-art extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (up to 5.4 , an average of 3.4 ), energy (up to 4.5 , an average of 3.2 ), and energy-delay products (up to 24.2 , an average of 12.6 ), while speeding up the design process significantly.

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Section: A Related Workmentioning

confidence: 99%

Custom-Instruction Synthesis for Extensible-Processor Platforms

Sun

Ravi²,

Raghunathan³

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Figure 4 declares the two queues, iq and rq. Line 3 contains the type declaration for instructions whose register operands have been fetched from the register 1 We chose here to present stalling for the sake of simplicity of the presentation.…”

Section: Three-stage Pipelined Speci£cationmentioning

confidence: 99%

“…Most of this work is primarily concerned with functional pipelining. Many synthesis tools target instruction-set architectures [10,4,3,14,15,1,9,2]; our tool, on the other hand, targets the more general class of sequential circuits. Other approaches start with a C program [8,5].…”

Section: Related Workmentioning

confidence: 99%

High-level automatic pipelining for sequential circuits

Marinescu¹,

Rinard²

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation.We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.

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“…Recently synthesis of application-specific programmable processors (ASPP) [Breternitz and Shen 1990;Guerra et al 1993] and applicationspecific instruction sets processors (ASIP) [Leupers et al 1994;Paulin et al 1994;Goosens et al 1995] received a great deal of attention in the CAD community. While both ASPPs and ASIPs and the technique proposed in this paper target implementation of several processes on the same processor, similarities between the two domains is very limited due to the different operational modes of the processors and the different nature of timing constraints.…”

Section: Related Workmentioning

confidence: 99%

A methodology and algorithms for the design of hard real-time multitasking ASICs

Potkonjak

Wolf

1999

ACM Trans. Des. Autom. Electron. Syst.

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Traditional high-level synthesis concentrates on the implementation of a single task (e.g. filter, linear controller, A/D converter). However, many applications-multifunctional embedded controllers, intelligent wireless end-points, and DSP and multimedia servers-are defined as sets of several computational tasks. This paper describes new techniques for the synthesis of ASIC implementations that realize multiple computational processes under hard real-time constraints. Our synthesis methodology establishes connections between two important computer engineering domains: operating systems and behavioral synthesis. Our hierarchical approach starts from an incompletely-specified preliminary solution and uses, interchangeably, operating system and behavioral synthesis techniques to derive increasingly more detailed and accurate design solutions. We have experimented with both optimal and heuristic algorithms to implement this methodology. The optimal algorithm uses several heuristics to speed up the average run time of an exhaustive branch-and-bound search. Force-directed optimization is the core of the heuristic synthesis method. Analysis of the proposed algorithms and the experiments shows that matching the number of bits and type of operations in tasks assigned to the same application-specific processor was the most important factor in obtaining area-efficient designs.

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Architecture synthesis of high-performance application-specific processors

Cited by 20 publications

References 11 publications

Custom-Instruction Synthesis for Extensible-Processor Platforms

Custom-Instruction Synthesis for Extensible-Processor Platforms

High-level automatic pipelining for sequential circuits

A methodology and algorithms for the design of hard real-time multitasking ASICs

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