Architecture optimizations for synchronization and communication on chip multiprocessors

Abstract

Chip multiprocessors (CMPs) enable concurrent execution of multiple threads using several cores on a die. Current CMPs behave much like symmetric multiprocessors and do not take advantage of the proximity between cores to improve synchronization and communication between concurrent threads. Thread synchronization and communication instead use memory/cache interactions. We propose two architectural enhancements to support fine grain synchronization and communication between threads that reduce overhead and memory/cache contention. RegisterBased Synchronization exploits the proximity between cores to provide low-latency shared registers for synchronization. This approach can save significant power over spin waiting when blocking events that suspend the core are used. Prepushing provides software controlled data forwarding between caches to reduce coherence traffic and improve cache latency and hit rates. We explore the behavior of these approaches, and evaluate their effectiveness at improving synchronization and communication performance on CMPs with private caches. Our simulation results show significant reduction in inter-core traffic, latencies, and miss rates.

Accelerating synchronization communications for high-density blade enclosure

“…They have been using customized fullempty-bit memory system to support full-system fine-grained synchronizations [5][6][7][8]. Also, some work is dedicated to accelerating on-chip fine-grained synchronization [9][10][11]. They modified the ISA of processors and used special instructions to support the fine-grained synchronization.…”

HPP controller: a system controller for high performance computing

“…The benefits of accelerating fine-grain synchronization have previously been discussed in detail [9][10][11][12][13][14][15] and some implementations are tested in software simulators or some real machines [4,9,16]. In these implementations, they either require a separate tag space for each value in the real memory, which requires a customized storage system and customized processors, or only support fine-grained synchronization in a single processor.…”