Architecture for Protecting Critical Secrets in Microprocessors

Lee, Ruby B.; Kwan, Peter C. S.; McGregor, J.P.; Dwoskin, Jeffrey; Wang, Zhenghong

doi:10.1145/1080695.1069971

Cited by 59 publications

(39 citation statements)

References 18 publications

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“…Partitioning: Many secure caches partition the cache lines (tag and data) between the victim and the attacker [23]- [26], [47], but the replacement policy and state is not considered and specified. For example, in Partition-Locked (PL) cache [24], each cache line is extended with one lock bit.…”

Section: B Lru Attack and Secure Cachesmentioning

confidence: 99%

Leaking Information Through Cache LRU States

Xiong

Szefer

2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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The widely deployed Least-Recently Used (LRU) cache replacement policy and its variants are an essential component of modern processors. However, we show for the first time in detail that the LRU states of caches can be used to leak information. The LRU states are shared among all the software that accesses the cache and we show that timing-based channels are possible: any access to a cache by a sender will modify the LRU states, and the receiver is able to observe this through a timing measurement. This paper presents LRU timing-based channels both when the sender and the receiver have shared memory, e.g., shared library data pages, and when they are fully separate processes without shared memory. In addition, the new LRU timing-based channels are demonstrated on both Intel and AMD processors in scenarios where the sender and the receiver are sharing the cache in both hyper-threaded setting and timesliced setting. The transmission rate of the new LRU channel can be up to 600Kbits/s per cache set in the hyper-threaded setting. Different from the existing cache channels which require the sender to have cache misses, the new LRU channels work with cache hits, making the channel faster and more stealthy as no cache misses are required for the sender. This paper also demonstrates that the new LRU channels can be used in transient execution attacks, e.g., Spectre, to retrieve the victim's secret. Further, this paper presents evaluation showing that the LRU channels also pose threats to existing secure cache designs. Possible defenses against the LRU timing-based channels are discussed and evaluated in simulation, with defense features added to protect the LRU states.

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Section: B Lru Attack and Secure Cachesmentioning

confidence: 99%

Leaking Information Through Cache LRU States

Xiong

Szefer

2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…There are a number of other works that provide isolated environments for trusted software modules [Lie et al 2000;Suh et al 2003;Lee et al 2005;Dwoskin and Lee 2007;McKeen et al 2013;Anati et al 2013;Hoekstra et al 2013;Boivie 2012;Owusu et al 2013;Evtyushkin et al 2014]. Haven [Baumann et al 2014] demonstrated a system to achieve protected execution on unmodified binaries using SGX hardware support [McKeen et al 2013].…”

Section: Hardware-supported Approachesmentioning

confidence: 99%

Rethinking Memory Permissions for Protection Against Cross-Layer Attacks

Elwell

Riley

Abu-Ghazaleh

et al. 2015

ACM Trans. Archit. Code Optim.

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The inclusive permissions structure (e.g., the Intel ring model) of modern commodity CPUs provides privileged system software layers with arbitrary permissions to access and modify client processes, allowing them to manage these clients and the system resources efficiently. Unfortunately, these inclusive permissions allow a compromised high-privileged software layer to perform arbitrary malicious activities. In this article, our goal is to prevent attacks that cross system layers while maintaining the abilities of system software to manage the system and allocate resources. In particular, we present a hardware-supported page permission framework for physical pages that is based on the concept of noninclusive sets of memory permissions for different layers of system software (such as hypervisors, operating systems, and user-level applications). Instead of viewing privilege levels as an ordered hierarchy with each successive level being more privileged, we view them as distinct levels each with its own set of permissions. In order to enable system software to manage client processes, we define a set of legal permission transitions that support resource allocation but preserve security. We show that the model prevents a range of recent attacks. We also show that it can be implemented with negligible performance overhead (both at load time and at runtime), low hardware complexity, and minimal changes to the commodity OS and hypervisor code.

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“…Architectural support for VM security. There have been architectural solutions to protecting applications and data from powerful software attacks [43,44]. Recent efforts [45,46] try to address this issue by means of architectural support.…”

Section: Related Workmentioning

confidence: 99%

Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment

Wen

Lee

Liu

et al. 2013

Proceedings of the ACM International Conference on Computing Frontiers

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Virtualization is fundamental to cloud computing because it allows multiple operating systems to run simultaneously on a physical machine. However, it also brings a range of security/privacy problems. One particularly challenging and important problem is: how can we protect the Virtual Machines (VMs) from being attacked by Virtual Machine Monitors (VMMs) and/or by the cloud vendors when they are not trusted? In this paper, we propose an architectural solution to the above problem in multi-processor cloud environments. Our key idea is to exploit hardware mechanisms to enforce access control over the shared resources (e.g., memory spaces), while protecting VM memory integrity as well as inter-processor communications and data sharing. We evaluate the solution using full-system emulation and cycle-based architecture models. Experiments based on 20 benchmark applications show that the performance overhead is 1.5%-10% when access control is enforced, and 9%-19% when VM memory is encrypted.

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Architecture for Protecting Critical Secrets in Microprocessors

Abstract: We propose "secret-protected (SP)

Cited by 59 publications

References 18 publications

Leaking Information Through Cache LRU States

Leaking Information Through Cache LRU States

Rethinking Memory Permissions for Protection Against Cross-Layer Attacks

Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment

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