Architecture and implementation of Vulcan

Stunkel, Craig B.; Denneau, Monty; Nathanson, B.J.; Shea, Dennis G.; Hochschild, Peter; Tsao, M.; Abali, Bülent; Joseph, Douglas J.; Varker, Philip

doi:10.1109/ipps.1994.288290

Cited by 54 publications

(19 citation statements)

References 13 publications

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“…This problem is exacerbated when deep buffers (to hold multiple flits and improve latencies) are used. Therefore, IBMs Vulcan network provides centralized flit buffers in each router to improve performance [42]. Each Vulcan switch has a central queue of 1,024 bytes shared by all the eight incoming channels.…”

mentioning

confidence: 99%

A framework for designing deadlock-free wormhole routing algorithms

Boppana

Chalasani

1996

IEEE Trans. Parallel Distrib. Syst.

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Abstract-This paper presents a framework to design fully-adaptive, deadlock-free wormhole algorithms for a variety of network topologies. The main theoretical contributions are (a) design of new wormhole algorithms using store-and-forward algorithms, (b) a sufficient condition for deadlock free routing by the wormhole algorithms so designed, and (c) a sufficient condition for deadlock free routing by these wormhole algorithms with centralized flit buffers shared among multiple channels. To illustrate the theory, several wormhole algorithms based on store-and-forward hop schemes are designed. The hop-based wormhole algorithms can be applied to a variety of networks including torus, mesh, de Brujin, and a class of Cayley networks, with the best known bounds on virtual channels for minimal routing on the last two classes of networks. An analysis of the resource requirements and performances of a proposed algorithm, called negative-hop algorithm, with some of the previously proposed algorithms for torus and mesh networks is presented.

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mentioning

confidence: 99%

A framework for designing deadlock-free wormhole routing algorithms

Boppana

Chalasani

1996

IEEE Trans. Parallel Distrib. Syst.

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“…Some proposals to provide high memory performance with lower cost include interleaved and wide memories. Such approaches have also been used in network routers such as the "Knockout Switch" [28] and the "Vulcan Switch" from IBM [24]. However, interleaved or wide memories have a serious drawback as it is necessary to wait for the reception of a wide word (in this context, a packet) before it can be written into memory.…”

Section: Avoiding Head-of-line Blockingmentioning

confidence: 99%

On the design of a high-performance adaptive router for CC-NUMA multiprocessors

Puente

Gregorio

Beivide

et al. 2003

IEEE Trans. Parallel Distrib. Syst.

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Abstract-This work presents the design and evaluation of an adaptive packet router aimed at supporting CC-NUMA traffic. We exploit a simple and efficient packet injection mechanism to avoid deadlock, which leads to a fully adaptive routing by employing only three virtual channels. In addition, we selectively use output buffers for implementing the most utilized virtual paths in order to reduce head-of-line blocking. The careful implementation of these features has resulted in a good trade off between network performance and hardware cost. The outcome of this research is a High-Performance Adaptive Router (HPAR), which adequately balances the needs of parallel applications: minimal network latency at low loads and high throughput at heavy loads. The paper includes an evaluation process in which HPAR is compared with other adaptive routers using FIFO input buffering, with or without additional virtual channels to reduce head-of-line blocking. This evaluation contemplates both the VLSI costs of each router and their performance under synthetic and real application workloads. To make the comparison fair, all the routers use the same efficient deadlock avoidance mechanism. In all the experiments, HPAR exhibited the best response among all the routers tested. The throughput gains ranged from 10 percent to 40 percent in respect to its most direct rival, which employs more hardware resources. Other results shown that HPAR achieves up to 83 percent of its theoretical maximum throughput under random traffic and up to 70 percent when running real applications. Moreover, the observed packet latencies were comparable to those exhibited by simpler routers. Therefore, HPAR can be considered as a suitable candidate to implement packet interchange in next generations of CC-NUMA multiprocessors.

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“…(A related model, the LogP model [17], was also proposed recently to address similar goals.) Systems that are well modeled by the postal model include parallel computers like TMC's CM-5 [24] and IBM's SP-2 [28], and communication networks such as PARIS [ 141 and AURORA [ 151. Bruck et al has confirmed experimentally in [IO] that a properly tuned broadcast based on the postal model on the Delta system can improve the best known implementation by more than 20%.…”

Section: Kipnis@haifasc3vnetibmcommentioning

confidence: 99%

Computing global combine operations in the multi-port postal model

Bar-Noy

Bruck

et al.

Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing

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Abstract-Consider a message-passing system of n processors, in which each processor holds one piece of data initially. The goal is to compute an associative and commutative reduction function on the n pieces of data and to make the result known to all the n processors. This operation is frequently used in many message-passing systems and is typically referred to as global combine, census computation, or gossiping. This paper explores the problem of global combine in the multiport postal model. This model is characterized by three parameters: n-the number of processors, k-the number of ports per processor, and &the communication latency. In this model, in every round r, each processor can send k distinct messages to k other processors, and it can receive k messages that were sent from k other processors 1 -1 rounds earlier. This paper provides an optimal algorithm for the global combine problem that requires the least number of communication rounds and minimizes the time spent by any processor in sending and receiving messages.

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Architecture and implementation of Vulcan

Cited by 54 publications

References 13 publications

A framework for designing deadlock-free wormhole routing algorithms

A framework for designing deadlock-free wormhole routing algorithms

On the design of a high-performance adaptive router for CC-NUMA multiprocessors

Computing global combine operations in the multi-port postal model

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