Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

Ahmed, Akram Ben; Abdallah, Abderazek Ben

doi:10.1007/s11227-013-0940-9

Cited by 45 publications

(31 citation statements)

References 27 publications

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“…The router is considered as the back-bone element in the whole ECN design. The ECN's router architecture is based upon OASIS NoC router (ONoC Router) [3], [9] with the addition of the optical switches arbitration module. Figure 1 illustrates ECN 's router architecture .…”

Section: A Electronic Control Network (Ecn)mentioning

confidence: 99%

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Ahmed

Meyer

Okuyama

et al. 2015

2015 2nd International Conference on Information Science and Control Engineering

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Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication.In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC) 1 . In addition, we present detailed complexity and performance evaluation of the proposed architecture.

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Section: A Electronic Control Network (Ecn)mentioning

confidence: 99%

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Ahmed

Meyer

Okuyama

et al. 2015

2015 2nd International Conference on Information Science and Control Engineering

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“…There are many different forms of NoC architecture out in development [6], [4], [14], [15], [16]. Most of these do not address fault issues within switches.…”

Section: Related Workmentioning

confidence: 99%

“…Others do not even address the issue of the throughput limitation of electrical signals. 3D-OASIS [15] and the original mesh [14] architecture both resort to using electrical interconnects, which have been proven to have lower throughput than their optical alternative. Additionally, optical data requires less power per bit [5].This new technology is not 100% beneficial, as can be seen with the results of certain optical NoCs.…”

Section: Related Workmentioning

confidence: 99%

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FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems

Meyer

Ahmed

Okuyama

et al. 2015

2015 IEEE 9th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip

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Photonic Networks-on-Chip (PNoCs) have been proposed as a disruptive technology solution to the silicon problem showing their great superiority over their electronic counterparts. In these architectures, higher bandwidth can be achieved thanks to the light speed transmissions, and the power required to transmit over a distance is much lower. Despite these advantages, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems.In this paper, we present a fault-tolerant optical router, named FTTDOR, with its electrical control module for highlyreliable low-power 3D-Networks-on-Chip (PHENIC). It uses minimal redundancy to assure accuracy of the packet transmission even after faulty Microring Resonators (MRs) are detected. The fault-tolerant optical switch is decomposed nonblocking, with minimal MRs, and requires no MRs for straight transmission (East to West, North to South, and Up to Down, as well as their inverses). Simulation results show that the network can maintain 98% and 94% throughput when considering 3% and 20% fault-rates, respectively. These results come with 35% decrease in the number of MRs when compared to the conventional crossbar switch resulting in 32% power reduction.

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“…Global interconnects are becoming the principal performance bottleneck for high performance Systems-on-Chip (SoCs) [2]. The 3-dimensional Networks-on-Chip (3D-NoCs) have been proposed as a promising architecture that combines the high parallelism of Network-on-Chip paradigm with the high performance and lower interconnect power of 3-dimensional integration circuits (3D-ICs) [6]. In the past few years, the benefits of 3D Integrated Circuits (3D-ICs) and mesh-based Network-on-Chips (NoCs) have been fused into a promising architecture opening a new horizon for IC design.…”

Section: Introductionmentioning

confidence: 99%

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

et al. 2017

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The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO) 1 . With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining powerefficient.

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Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

Cited by 45 publications

References 27 publications

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

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