Architecture and design of AlphaServer GS320

Gharachorloo, Kourosh; Sharma, Mandeep; Steely, Simon C.; Doren, Stephen Van

doi:10.1145/378993.378997

Cited by 83 publications

(39 citation statements)

References 26 publications

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“…The main source of increased latency for the tree barrier using coherent variables, is that a barrier Receivers polling for these signals introduce multiple round-trips through the directory to each signal propagation. For both MCS barriers and locks, one can expect that aggressive non-blocking coherence protocols [8] and migratory sharing optimizations can reduce the latency of contended flag update-reclaim interactions (atomic or not), but communication operations in these algorithms are dependent on each other and will introduce serialization of miss overhead. Explicit communication advocated here can significantly reduce such overheads.…”

Section: Performance On the Hardware Prototypementioning

confidence: 99%

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Kavadias

Katevenis

Zampetakis

et al. 2011

Int J Parallel Prog

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Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds -the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the 123Int J Parallel Prog performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

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Section: Performance On the Hardware Prototypementioning

confidence: 99%

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Kavadias

Katevenis

Zampetakis

et al. 2011

Int J Parallel Prog

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“…All modern DSM multiprocessors with hardware cache coherence that we are aware of provide a NUMA-aware data placement interface to the user, so that the user can explicitly place pages on specific nodes. For example, on the Compaq GS320 [7], a system which does not have hardware page access counters, it is possible to use the NUMA APIs of Tru64 UNIX and obtain accurate information on the placement of ranges of virtual addresses in physical memory. Given this information, software instrumentation for access tracing is possible.…”

Section: Implementation Issuesmentioning

confidence: 99%

Quantifying contention and balancing memory load on hardware DSM multiprocessors

Nikolopoulos

2003

Journal of Parallel and Distributed Computing

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This paper makes the following contributions: It proposes a new methodology for quantifying remote memory access contention on hardware DSM multiprocessors. The most valuable aspect of this methodology is that it assesses the overhead of contention on real parallel programs running on real hardware. The methodology uses as input the number of accesses from each node of the DSM to each page in memory. A trace of the memory accesses of the program obtained at runtime is used to compute a fairly accurate estimate of the fraction of execution time wasted due to contention. The paper presents also a new algorithm which detects potential hot spots in pages and balances memory load using dynamic page migration. The algorithm attacks indirectly the problem of contention by balancing the remote memory access latency across the nodes of the system. Experiments with five irregular parallel codes on a 128-processor Origin2000 show that the algorithm yields significant performance improvements.

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“…Note that this is necessary only because the Stanford FLASH protocol collects invalidation acknowledgments at the home node. The AlphaServer GS320 [7] uses a three-lane protocol. The virtual lanes are named Q0, Q1, and Q2.…”

Section: Introductionmentioning

confidence: 99%

Exploring virtual network selection algorithms in DSM cache coherence protocols

Chaudhuri

Heinrich

2004

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Distributed shared memory (DSM) multiprocessors typically require disjoint networks for deadlock-free execution of cache coherence protocols. This is normally achieved by implementing virtual networks with the help of virtual channels or virtual lanes multiplexed on a single physical network. To keep the coherence protocol simple, messages are usually assigned to virtual lanes in a predefined static manner based on a cycle-free lane assignment dependence graph. However, this static split of virtual networks (such as request and reply networks) may lead to underutilization of certain virtual networks while saturating the other networks. In this paper, we explore different static and dynamic schemes to select the virtual lanes for outgoing messages and mix the load among them without restricting any particular type of message to be carried only by a particular virtual network. We achieve this by exposing the selection algorithms to the coherence protocol itself, so that it can inject messages into selected virtual lanes based on some local information, and still enjoy deadlock-freedom. Our execution-driven simulation on five applications from the SPLASH-2 suite shows that as the system scales, the virtual network selection algorithms play an important role. For 128-node systems, our dynamic selection algorithm speeds up parallel execution by as much as 22 percent over an optimized baseline system running a modified SGI Origin 2000 protocol. We also explore how network latency, the number of message buffers per virtual lane, and the depth of network interface output queues affect the relative performance of various virtual lane selection algorithms.

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Architecture and design of AlphaServer GS320

Cited by 83 publications

References 26 publications

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Quantifying contention and balancing memory load on hardware DSM multiprocessors

Exploring virtual network selection algorithms in DSM cache coherence protocols

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