Architecture and Design Flow for a Highly Efficient Structured ASIC

Ho, Man-Ho; Ai, Yanqing; Chau, Thomas; Yuen, Sze-Kit; Choy, Chiu-Sing; Leong, Philip H. W.; Pun, Kong-Pang

doi:10.1109/tvlsi.2012.2190478

Cited by 15 publications

(4 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…According to [31], FPGAs with embedded multipliers and block memories require on average 7 times more power compared with ASICs, for the same circuit design. However, the increased nonrecurring engineering cost makes low to midvolume ASIC production unaffordable [32]. In addition, systems based on energy harvesting usually are deployed in the wide and remote areas.…”

Section: A Simulation Frameworkmentioning

confidence: 99%

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

Liu

Mak

Zhang

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Through energy harvesting system, new energy sources are made available immediately for many advanced applications based on environmentally embedded systems. However, the harvested power, such as the solar energy, varies significantly under different ambient conditions, which in turn affects the energy conversion efficiency. In this paper, we propose an approach for designing power-adaptive computing systems to maximize the energy utilization under variable solar power supply. Using the geometric programming technique, the proposed approach can generate a customized parallel computing structure effectively. Then, based on the prediction of the solar energy in the future time slots by a multilayer perceptron neural network, a convex model-based adaptation strategy is used to modulate the power behavior of the real-time computing system. The developed power-adaptive computing system is implemented on the hardware and evaluated by a solar harvesting system simulation framework for five applications. The results show that the developed power-adaptive systems can track the variable power supply better. The harvested solar energy utilization efficiency is 2.46 times better than the conventional static designs and the rule-based adaptation approaches. Taken together, the present thorough design approach for self-powered embedded computing systems has a better utilization of ambient energy sources.

show abstract

Section: A Simulation Frameworkmentioning

confidence: 99%

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

Liu

Mak

Zhang

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Since block RAM is highly optimized in terms of area, we multiply the number of slices it consumes with a factor of 1/35. This is because it is observed that FPGA on average consumes 35 times more area than an ASIC platform which is highly optimized for area [8]. Therefore, the hardware resources consumed by one block RAM equals (72 slices) × percentage of block RAM occupied × 1/35.…”

Section: Performance Metricsmentioning

confidence: 99%

High throughput and programmable online trafficclassifier on FPGA

Tong

Sun

Matam

et al. 2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

Machine learning (ML) algorithms have been shown to be effective in classifying the dynamic internet traffic today. Using additional features and sophisticated ML techniques can improve accuracy and can classify a broad range of application classes. Realizing such classifiers to meet high data rates is challenging. In this paper, we propose two architectures to realize complete online traffic classifier using flowlevel features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL discretization algorithm. It achieves an accuracy of 97.92% when classifying a traffic trace consisting of eight application classes. Next, we accelerate our classifier using two architectures on FPGA. One architecture stores the classifier in on-chip distributed RAM. It is designed to sustain a high throughput. The other architecture stores the classifier in block RAM. It is designed to operate with small hardware footprint and thus built at low hardware cost. Experimental results show that our high throughput architecture can sustain a throughput of 550 Gbps assuming 40 Byte packet size. Our low cost architecture demonstrates a 22% better resource efficiency than the high throughput design. It can be easily replicated to achieve 449 Gbps while supporting 160 input traffic streams concurrently. Both architectures are parameterizable and programmable to support any binary-tree-based traffic classifier. We develop a tool which allows users to easily map a binary-tree-based classifier to hardware. The tool takes a classifier as input and automatically generates the Verilog code for the corresponding hardware architecture.

show abstract

“…Most of the existing CaSeAs suffer from carry propagation in their internal RCA blocks, and few have area constraint problems. From the study of previous work on CaSeA, the cell regularity and uniform structure of the final design plays a vital role in the physical design of ASIC [20][21][22]. The back-end design can be made simpler with cell regularity concept [23,24], and [25].…”

Section: Introductionmentioning

confidence: 99%

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

View full text Add to dashboard Cite

This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

show abstract

Architecture and Design Flow for a Highly Efficient Structured ASIC

Cited by 15 publications

References 21 publications

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

High throughput and programmable online trafficclassifier on FPGA

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Contact Info

Product

Resources

About