Architectural synthesis techniques for dynamically reconfigurable logic

Vasilko, Milan; Ait-Boudaoud, Djamel

doi:10.1007/3-540-61730-2_31

Cited by 23 publications

(19 citation statements)

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“…These include DFGs [40], mixed control data-flow graphs (CDFG) [38], timed decision tables (TDT) [33], and various flavors of graph-based and table-based formalisms sometimes augmented with global flow information such as module call graphs (MCG). Although these representations capture common features such as data and control dependencies among operations [29], they are not able to capture the temporal or functional locality among operations as well as the interconfiguration relationships.…”

Section: The Design Modelmentioning

confidence: 99%

“…2. Dynamic scheduling: find a schedule and a temporal partitioning for subsequent reconfigurations leading to the shortest execution time (including reconfiguration time) in a given total available area of DR FPGAs [41].…”

Section: The Synthesis Algorithm and The Optimization Strategiesmentioning

confidence: 99%

“…Currently, techniques to automatically partition designs temporally have extended existing scheduling and clustering techniques of high-level synthesis [15,17,31,37,40,41].…”

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

“…[40,41], and is based on a static-list scheduling heuristic enhanced to consider dynamic area constraint. The algorithm is executed in two phases.…”

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

“…The temporal partitioning tool heuristically estimates the upper bound on the number of temporal segments for building a Non-linear Programming (NLP) formulation. They use a variation of Bournemouth University's list-scheduling algorithm [40,41] for this estimation. The temporal partitioning problem is solved by an Integer Linear Programming (ILP) solver.…”

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

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A review of high-level synthesis for dynamically reconfigurable FPGAs

Zhang

2000

Microprocessors and Microsystems

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Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. The key to harnessing the power of DR FPGAs for most applications is to develop high-level synthesis tools for transforming automatically an algorithmic level behavioral specification into DR FPGA configurations. In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. The differences in high-level synthesis technology between classical systems and dynamically reconfigurable systems are discussed. Then, we describe the basic tasks in the high-level synthesis of dynamically reconfigurable systems. Finally, techniques that have been developed in the past few years for the high-level synthesis of dynamically reconfigurable systems are presented. ᭧

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Section: The Design Modelmentioning

confidence: 99%

Section: The Synthesis Algorithm and The Optimization Strategiesmentioning

confidence: 99%

“…Currently, techniques to automatically partition designs temporally have extended existing scheduling and clustering techniques of high-level synthesis [15,17,31,37,40,41].…”

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

“…[40,41], and is based on a static-list scheduling heuristic enhanced to consider dynamic area constraint. The algorithm is executed in two phases.…”

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

Section: Temporal Partitioning and Scheduling Techniquesmentioning

confidence: 99%

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