J Supercomput
 2015
DOI: 10.1007/s11227-015-1383-2
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Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems

Behram Khan
1
,
Daniel Goodman
2
,
Salman Khan3
et al.
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Cited by 3 publications
(1 citation statement)
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“…A estratégia prevista por este projeto utiliza o modelo a fluxo de dados em nível de compilação apenas, para a exploração otimizada de paralelismo em estruturas convencionais. 40,41…”
Section: Terafluxunclassified

πFlowMR - Uma nova arquitetura a fluxo de dados dinâmico, escalável e com múltiplos anéis, implementada em um cluster de FPGAs de baixo custo

Junior1
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“…A estratégia prevista por este projeto utiliza o modelo a fluxo de dados em nível de compilação apenas, para a exploração otimizada de paralelismo em estruturas convencionais. 40,41…”
Section: Terafluxunclassified

πFlowMR - Uma nova arquitetura a fluxo de dados dinâmico, escalável e com múltiplos anéis, implementada em um cluster de FPGAs de baixo custo

Junior1
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Data-Aware Task Dispatching for Batch Queuing System

Li
1
,
Tatebe
2
2017
IEEE Systems Journal
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Heidarshenas
1
,
Gangwani
2
,
Yesil
3
et al. 2020
Proceedings of the 34th ACM International Conference on Supercomputing
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