Architectural support for data-intensive applications

Abstract

The gap between the speed of logic and the DRAM memory access is widening. Traditional processors hide some of the mismatch in memory latency using techniques such as multi-level caches, instruction prefetching and memory interleaving. The bandwidth available at the system bus also forms a bottleneck; even an elaborate memory hierarchy with a perfect prefetching predictor generate memory traffic that overwhelms the capabilities of modern memory subsystems. A potential solution is the integration of DRAM and logic on the same die. Such solutions are motivated by the following: (i) the bandwidth available within the chip is many orders of magnitude higher than that at the memory bus at a significantly lower access time and with lower power dissipation; and (ii) as typical workloads shift towards data-intensive/multimedia applications, the wide bandwidth can be effectively utilized. However, there are significant challenges in developing architectures and programming models that expose the available bandwidth to end users. This paper presents the design of an intelligent memory based on a distributed data-parallel architecture with limited support for control parallelism (called PPIM). We investigate some of the relevant design issues and the success of such an architecture in supporting dataintensive applications. A cycle-accurate simulator is developed to study the architecture and performance for some data-intensive applications is compared against that of a modern superscalar processor (simulated using the simplescalar tool-set).