Architectural strategies for implementing an image processing algorithm on XC6000 FPGA

Heron, J.; Woods, Roger

doi:10.1007/3-540-61730-2_34

“…Other work which has been done in UK and relevant to this area of research has been presented in [23,24] where bit level systolic architectures have been developed to perform matrix -vector product used for DCT and other transforms computation. In addition, other architectures based on systolic and distributed arithmetic design methodologies have been developed in [11] for DCT, FFT and other transforms computation. Other systolic architectures and methodologies have been proposed in [18,19,20,21,22] for matrix product, Kalman filters and matrix factorisation.…”

Section: Previous Researchmentioning

confidence: 99%

“…Since their commercial introduction in the mid-1980's, FPGAs have been studied as a possible way of implementing matrix algorithms [10,11]. Over this period, these commodity digital parts have become components due to their ability to implement many different logic functions efficiently and their ability to be easily reconfigured as system hardware requirements change.…”

Section: Custom Computing Using Fpgamentioning

confidence: 99%

<title>FPGA-based coprocessor for matrix algorithms implementation</title>

Amira

¹

,

Bensaali

²

2003

SPIE Proceedings

0

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Matrix algorithms are important in many types of applications including image and signal processing. These areas require enormous computing power. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix operations such as matrix multiplication which is of O (N 3 ) on a sequential computer and O (N 3 /p) on a parallel system with p processors complexity. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using an FPGA based environment. Solutions for the problem of processing large matrices have been proposed. The proposed system architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.

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“…As one of the first, the XC6200 FPGA series allow the user to selectively modify the contents of configuration memory, socalled partial reconfiguration. There were several applications that utilize the partial reconfiguration feature of XC6200 [59] [62] communicate via a general routing matrix. This switch matrix comprises an array of routing switches located at the intersections of horizontal and vertical routing channels.…”

mentioning

confidence: 99%

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Chun¹

2021

Preprint

0

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Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

show abstract

“…As one of the first, the XC6200 FPGA series allow the user to selectively modify the contents of configuration memory, socalled partial reconfiguration. There were several applications that utilize the partial reconfiguration feature of XC6200 [59] [62] communicate via a general routing matrix. This switch matrix comprises an array of routing switches located at the intersections of horizontal and vertical routing channels.…”

mentioning

confidence: 99%

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Chun¹

2021

Preprint

0

View full text Add to dashboard Cite

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

show abstract

Architectural strategies for implementing an image processing algorithm on XC6000 FPGA

Cited by 9 publications

References 2 publications

<title>FPGA-based coprocessor for matrix algorithms implementation</title>

<title>FPGA-based coprocessor for matrix algorithms implementation</title>

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

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