Architectural simulation in the context of behavioral synthesis

Jemai, Abderrazak; Kission, P.; Jerraya, A.A.

doi:10.1109/date.1998.655918

Cited by 2 publications

(5 citation statements)

References 7 publications

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“…The resulting Hw-Sw co-design environment is an application-driven tool-chain able to evaluate and to modify both Sw and Hw. The software developer challenge is often to optimize a communication-standardbased multimedia application [15,16] to get real time performance on a given architecture family. The best result, following the above constraints list, is achievable tuning both the algorithm implementation and architectural features.…”

Section: Main Issue and Related Workmentioning

confidence: 99%

“…In AMIS [15,16] architectural simulation flexibility is obtained through the use of the abstract architecture (internal model of behavioral synthesis): an intermediate representation between behavioral and RTL description. In the SPADE [17] methodology a design technology that helps designer to define heterogeneous architecture starting from a set of target applications is described.…”

Section: Simulation Flexibilitymentioning

confidence: 99%

“…In other words, development environment features in terms of debug-profile support and connectivity to other tool chain modules represent a fundamental requirement in judging an HwSw co-design simulation environment [27]. In AMI-CAL [16] functionality and user interface are tailored to work in cooperation with a high level synthesis.…”

Section: Development Toolsmentioning

confidence: 99%

See 2 more Smart Citations

A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

Barbieri

Bariani

Cabitto

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-design environments [2]. VLIW architecture allows generating optimized machine code from high-level languages exploiting Instruction Level Parallelism (ILP) [3]. Furthermore, applications requirements and time to market constraints are growing dramatically moving functionalities toward System on Chip (SoC) direction. This paper presents VLIW-SIM, an Application-Driven Architecture-design approach based on Instruction Set simulation. VLIW architectures and Instruction Set simulation were chosen to fulfill multimedia domain requirements and to implement an efficient Hw-Sw co-design environment. The VLIW-SIM simulation technology is based on pipeline status modeling, Simulation cache and Simulation Oriented Hw description. An effective support for Hw-Sw co-design requires high simulation performance (in terms of Simulated Instruction per Second-SIPS), flexibility (the ability to represent a number of different architectures) and cycle accuracy. There is a strong trade-off between these features: cycle accurate or close to cycle accurate simulation have usually low performance [4,5]. Good simulation performance can be obtained loosing the simulator flexibility. Moreover SoC simulation requires a further degree of flexibility in simulating different components (core, co-processors, memories, buses). The proposed approach is focused on interpretative (not compiled [6]) re-configurable Instruction Set Simulator (ISS) in order to support both application design and architecture exploration. VLIW-SIM main features are: efficient host resource allocation, Instruction Set and Architecture description Flexibility (Instruction Set Dynamic Generation and Simulation Oriented Hardware Description), Step by step pipeline status tracking, Simulation Speed and Accuracy. Performance of simulation test for three validation case studies (TI TMS320C62x, TI TMS320C64x and ST200) are reported.

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Section: Main Issue and Related Workmentioning

confidence: 99%

Section: Simulation Flexibilitymentioning

confidence: 99%

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A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

Barbieri

Bariani

Cabitto

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

show abstract

“…The software developer challenge is often to optimize a standard-based multimedia application [11,12] to get real-time performance on a given architecture. The best result, following a given design constraints list, is achievable by tuning both the algorithm implementation and architectural features.…”

Section: Main Issue and Related Workmentioning

confidence: 99%

“…An efficient HW-SW codesign development environment should also allow continuous access to registers and bus values during the simulation providing statistics about the use of the different resources [11]. The capability to collect statistics on both system devices, for example, internal resource utilization, and interdevice communications allows a software developer to better focus his work either on a particular application or on a portion of the selected code.…”

Section: Main Issue and Related Workmentioning

confidence: 99%

Multimedia Terminal System-on-Chip Design and Simulation

Barbieri

Bariani

Scotto

et al. 2005

EURASIP J. Adv. Signal Process.

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This paper proposes a design approach based on integrated architectural and system-on-chip (SoC) simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW) digital signal processors (DSPs), the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA) simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

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Architectural simulation in the context of behavioral synthesis

Abstract: Abstract

Cited by 2 publications

References 7 publications

A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

Multimedia Terminal System-on-Chip Design and Simulation

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