Architectural investigation of matrix data layout on multicore processors

Kim, Minwoo; Ro, Won Woo

doi:10.1016/j.future.2013.10.020

Cited by 4 publications

(1 citation statement)

References 41 publications

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“…The authors of [3] compared the speed of the CPU and GPU on systems working with daylight, and provided a better algorithm than the CPU in GPU environments in OpenCL. [4] is about the hardware architecture of matrix multiplication on real multi-core systems. The authors considered the system data as data matrices and tried to find a better destination for temporary system data in multi-layer cashes.…”

Section: Related Workmentioning

confidence: 99%

Optimization Method to Reduce Matrices Multiplications in the Context of CUDA

Khatibi¹,

Khatibi²

2018

IJCA

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Parallel programming is an effective way to increase the speed of processing applications. It is carried out simultaneously by multiple processors rather than by a single processor. We compare the number of necessary calculations for multiplying the chain matrix in normal mode with the parallel mode. Since we used the famous parallel language named CUDA in our program, we will first present a brief description of the language and secondly, we explain essential mathematical notions and compare the performance of both programs.

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Section: Related Workmentioning

confidence: 99%

Optimization Method to Reduce Matrices Multiplications in the Context of CUDA

Khatibi¹,

Khatibi²

2018

IJCA

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Innovative methods and algorithms for advanced data-intensive computing

Cuzzocrea

2014

Future Generation Computer Systems

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Progressive Multicore RLNC Decoding With Online DAG Scheduling

2019

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A complete generation of packets coded with Random Linear Network Coding (RLNC) can be quickly decoded on a multicore system by scheduling the involved matrix block operations in parallel with an offline (pre-recorded) directed acyclic graph (DAG). The waiting for a complete generation of packets can be avoided with progressive RLNC decoding that commences the decoding (and can decode some packets) before all packets in a generation have been received. This article develops and evaluates a novel progressive RLNC decoding strategy based on the principle of DAG scheduling of parallel matrix block operations. The novel strategy involves helper matrices for conducting the Gauss Jordan elimination based on rows of blocks of matrix elements. The matrix block computations are dynamically scheduled by an online DAG which permits branching, e.g., to skip unnecessary matrix block operations. The throughput and delay of the novel progressive RLNC decoding strategy are evaluated with experiments on two heterogeneous multicore processor boards. The novel progressive RLNC decoding achieves throughput levels on par with stateof-the-art non-progressive (full-generation) RLNC decoding and achieves three times higher throughput than the fastest (highest-throughput) known progressive RLNC decoder for small generation sizes and short data packets. Also, our progressive RLNC decoding greatly reduces receiver delays for moderate to large generation sizes; the delay reductions are particularly pronounced when a low-delay RLNC version is employed (e.g., reduction to one tenth of the non-progressive decoding delay for a generation size of 256 packets). INDEX TERMS Directed acyclic graph (DAG), helper matrix, heterogeneous multicore architecture, online scheduling, parallel computing, random linear network coding (RLNC).

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Architectural investigation of matrix data layout on multicore processors

Cited by 4 publications

References 41 publications

Optimization Method to Reduce Matrices Multiplications in the Context of CUDA

Optimization Method to Reduce Matrices Multiplications in the Context of CUDA

Innovative methods and algorithms for advanced data-intensive computing

Progressive Multicore RLNC Decoding With Online DAG Scheduling

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