Proceedings of the 9th International Conference on Neural Information Processing, 2002. ICONIP '02.
DOI: 10.1109/iconip.2002.1198975
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Architectural improvements and FPGA implementation of a multimodel neuroprocessor

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“…Moreover, Vivado allows user to develop new logical blocks (user customized) by supporting VHDL and Verilog hardware description languages. After the design phase, the user has the possibility to simulate the design, analyse the results, synthesize it into FPGA, and finally run it directly on an FPGA device [29], [30]. The results presented in this paper were obtained using a Xilinx Spartan 7 FPGA device which is the highest density device in the Spartan-7 family [31].…”
Section: B Detailed Design Of Hardware E2e Modulementioning
confidence: 99%
“…Moreover, Vivado allows user to develop new logical blocks (user customized) by supporting VHDL and Verilog hardware description languages. After the design phase, the user has the possibility to simulate the design, analyse the results, synthesize it into FPGA, and finally run it directly on an FPGA device [29], [30]. The results presented in this paper were obtained using a Xilinx Spartan 7 FPGA device which is the highest density device in the Spartan-7 family [31].…”
Section: B Detailed Design Of Hardware E2e Modulementioning
confidence: 99%