Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor

Abstract

We have developed a quantum annealing processor, based on an array of tunably coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process [1]. Implementing this type of processor at a scale of 512 qubits and 1472 programmable inter-qubit couplers and operating at ∼ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular we will review some of the design trade-offs at play in the floor-planning of the physical layout, driven by the desire to have an algorithmically useful set of inter-qubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context we have developed a new ultra-low power embedded superconducting digital-to-analog flux converters (DACs) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux-DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ∼ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see for example [2]).

Degeneracy, degree, and heavy tails in quantum annealing

“…Qubits in a D-Wave processor are connected as a Chimera graph [22] (see Fig. 1), in which most qubits are coupled to six others, provided that only a few qubits and couplers are inoperable.…”

Constructing SAT Filters with a Quantum Annealer

“…This paper contains results from a D-Wave Two (DW2) quantum annealing processor using a Washington W3 chip operating over 1097 of 1152 configured qubits in a C 12 Chimera layout [4]. All runs use the minimum anneal time of 20µs.…”

Coherent Ising machines—optical neural networks operating at the quantum limit

“…[1][2][3][4] Another approach of contemporary interest is the adiabatic quantum computation (AQC) 5 and quantum annealing (QA). 6,7 Sophisticated AQC/QA devices are already under development, [8][9][10][11] but providing dense connectivity between qubits remains a major challenge 12 with serious implications for the efficiency of AQC/QA systems. 13 Networks of degenerate optical parametric oscillators (DOPOs) are an alternative physical system, with an unconventional operating mechanism, [14][15][16][17] for solving the Ising problem, [18][19][20] and by extension many other combinatorial optimization problems.…”