Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link

Raghavan, Leneesh; Wu, Ting

doi:10.1109/vlsi.design.2010.83

Cited by 12 publications

(5 citation statements)

References 2 publications

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“…Each FDE contains two inverters (INV1 and INV2) and a positive feedback control unit (PFCU). The cross-coupled inverters contribute significantly to providing insensitive properties to supply variations [28,29,30]. As shown in the FDE1 of Fig.…”

Section: Proposed Full-swing DCC Architecturementioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

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This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

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Section: Proposed Full-swing DCC Architecturementioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

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“…The traditional analog DCC circuit uses an analog integrator to detect the duty cycle error, but this can only be used in low speed applications [5]. The digital DCC uses two delay lines to correct the accuracy [6], [7]. This requires a very complicated circuit and results in relatively high power consumption [8].…”

Section: Ntroductionmentioning

confidence: 99%

Design of a High Frequency Duty-Cycle Corrector within 20%–80% Correction Range

Lin¹,

Hsu²

2019

IJIEE

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An analog duty cycle correction circuit using a novel pulse-width modification cell. We correct the duty-cycle by changing the phase of the voltage. Our calibration allows the input duty cycle to range from 20% to 80%, and the circuit corrects the duty cycle to 50%. The proposed circuit operation frequency is at 0.8GHz to 4GHz, and it correctes to less than 1% error.The duty-cycle correction circuit is implemented in a 1.8V, and 180nm CMOS technology at 25°C.

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“…Therefore, we should analyze the equivalent linear model of DCC before we design the feedback loop. Conventional DCCs usually adopt a first-order detection scheme, which only includes an integrator [2] or a filter [11]. Fig.…”

Section: Lpf and Dcdmentioning

confidence: 99%

“…Generally, DCCs can be categorized into analog, digital, and mixed-mode types [2]. The analog DCCs usually adopt negative feedback schemes, which can achieve higher accuracy but also lead to longer correction time [3], [4].…”

Section: Introductionmentioning

confidence: 99%

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector

Guo

Liu

Wang

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are used to support the DCC to work at a high frequency up to 20 GHz with a wide correction range from 20% to 80%. On the feedback path, a second order duty cycle detector scheme is adopted including a low pass filter and an integrator to significantly reduce the jitter in the output clock and ensure high correction accuracy. Through simulation using 65 nm TSMC CMOS technology, the output duty cycle is corrected to 50±0.3% over the input duty-cycle range of 20-80% for 12.5-20 GHz. The DCC consumes 5.2 mW at 16 GHz using a 1.0 V supply voltage, and has a 572 fs peak-to-peak jitter and a 249 fs RMS jitter.

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Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link

Cited by 12 publications

References 2 publications

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Design of a High Frequency Duty-Cycle Corrector within 20%–80% Correction Range

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector

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