Architecting hierarchical coherence protocols for push-button parametric verification

Matthews, Opeoluwa; Sorin, Daniel J.

doi:10.1145/3123939.3123971

Cited by 5 publications

(3 citation statements)

References 31 publications

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“…On NUMA architectures, memory hierarchy-aware locks further optimize cache-coherence traffic by prioritizing intra-NUMA node communication over inter-NUMA node communication [6][7][8][9][10]. While GCS builds on queue-based locks, hierarchical locks are orthogonal to our generalized cache coherence -indeed, we can generalize hierarchical cache-coherence protocols [60][61][62] to achieve similar prioritization of requestors on the same compute blade.…”

Section: Related Workmentioning

confidence: 99%

GCS: Generalized Cache Coherence For Efficient Synchronization

Yu¹,

Lee²,

Khandelwal³

et al. 2023

Preprint

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We explore the design of scalable synchronization primitives for disaggregated shared memory. Porting existing synchronization primitives to disaggregated shared memory results in poor scalability with the number of application threads because these primitives are layered atop cache-coherence substrates, which engenders redundant inter-core communications. High cache-coherence latency (µs) with low bandwidths in state-of-the-art disaggregated shared memory designs amplifies the impact of such redundant communications and precludes scalability.In this work, we argue for a co-design for the cachecoherence and synchronization layers for better performance scaling of multi-threaded applications on disaggregated memory. This is driven by our observation that synchronization primitives are essentially a generalization of cache-coherence protocols in time and space. We present GCS as an implementation of this co-design. GCS employs wait queues and arbitrarily-sized cache lines directly at the cache-coherence layer for temporal and spatial generalization, respectively. We evaluate GCS against the layered approach for synchronization primitives -the pthread implementation of readerwriter lock -and show that GCS improves in-memory keyvalue store performance at scale by 1 − 2 orders of magnitude.

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Section: Related Workmentioning

confidence: 99%

GCS: Generalized Cache Coherence For Efficient Synchronization

Yu¹,

Lee²,

Khandelwal³

et al. 2023

Preprint

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“…Verifiability can ensure that the bugs that are likely to be introduced during manual protocol design are caught, but verifiability does not necessarily simplify the design process. Verifiable hierarchical protocols include HCC [6], Fractal Coherence [10], and protocols that conform to the Neo framework Neo [9].…”

Section: Related Workmentioning

confidence: 99%

“…Crucially, communication between levels of the hierarchy must preserve coherence invariants. In addition to the design complexity, verification is also more challenging with hierarchy, due primarily to the much larger state space [9], [12].…”

Section: Introductionmentioning

confidence: 99%

HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols

Oswald

Nagarajan

Sorin

2020

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

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We present HieraGen, a new tool for automatically generating hierarchical cache coherence protocols. HieraGen's inputs are the simple, atomic, stable state protocols for each level of the hierarchy. HieraGen's output is a highly concurrent hierarchical protocol, in the form of the finite state machines for all of the cache and directory controllers. HieraGen thus reduces the complexity that architects face, by offloading the challenging tasks of composing protocols and managing concurrency. Experiments show that HieraGen can automatically generate correct-by-construction MOESI family of hierarchical protocols with dozens of states and hundreds of transitions. We have verified all of the generated protocols for safety and deadlock freedom using a model checker.

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Hemiola: A DSL and Verification Tools to Guide Design and Proof of Hierarchical Cache-Coherence Protocols

Choi¹,

Chlipala²,

Arvind³

2022

Computer Aided Verification

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Cache-coherence protocols have been one of the greatest challenges in formal verification of hardware, due to their central complication of executing multiple memory-access transactions concurrently within a distributed message-passing system. In this paper, we introduce Hemiola, a framework embedded in Coq that guides the user to design protocols that never experience inconsistent interleavings while handling transactions concurrently. The framework provides a DSL, where any protocol designed in the DSL always satisfies the serializability property, allowing a user to verify the protocol assuming that transactions are executed one-at-a-time. Hemiola also provides a novel invariant proof method, for protocols designed in Hemiola, that only requires considering execution histories without interleaved memory accesses. We used Hemiola to design and prove hierarchical MSI and MESI protocols as case studies. We also demonstrated that the case-study protocols are hardware-synthesizable, by using a compilation/synthesis toolchain targeting FPGAs.

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Architecting hierarchical coherence protocols for push-button parametric verification

Cited by 5 publications

References 31 publications

GCS: Generalized Cache Coherence For Efficient Synchronization

GCS: Generalized Cache Coherence For Efficient Synchronization

HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols

Hemiola: A DSL and Verification Tools to Guide Design and Proof of Hierarchical Cache-Coherence Protocols

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