Architecting a chunk-based memory race recorder in modern CMPs

Pokam, Gilles; Pereira, Cristiano; Danne, Klaus; Kassa, Rolf; Adl-Tabatabai, Ali-Reza

doi:10.1145/1669112.1669183

Cited by 32 publications

(43 citation statements)

References 17 publications

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“…State-of-the-art proposals for hardware-assisted MRR record each processor's execution as a series of Chunks (also called Blocks or Episodes) of instructions executed between communications with other processors [3,9,10,18,19,[23][24][25]33]. The chunks of different processors are ordered in a graph based on inter-processor data dependences.…”

Section: Background On Chunk-based Recordingmentioning

confidence: 99%

RelaxReplay

Honarmand

Torrellas

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Record and Deterministic Replay (RnR) of multithreaded programs on relaxed-consistency multiprocessors has been a long-standing problem. While there are designs that work for Total Store Ordering (TSO), finding a general solution that is able to record the access reordering allowed by any relaxedconsistency model has proved challenging.This paper presents the first complete solution for hardware-assisted memory race recording that works for any relaxed-consistency model of current processors. With the scheme, called RelaxReplay, we can build an RnR system for any relaxed-consistency model and coherence protocol. RelaxReplay's core innovation is a new way of capturing memory access reordering. Each memory instruction goes through a post-completion in-order counting step that detects any reordering, and efficiently records it. We evaluate RelaxReplay with simulations of an 8-core release-consistent multicore running SPLASH-2 programs. We observe that RelaxReplay induces negligible overhead during recording. In addition, the average size of the log produced is comparable to the log sizes reported for existing solutions, and still very small compared to the memory bandwidth of modern machines. Finally, deterministic replay is efficient and needs minimal hardware support.

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Section: Background On Chunk-based Recordingmentioning

confidence: 99%

RelaxReplay

Honarmand

Torrellas

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Regarding capturing and enforcing inter-thread dependences, while our approach builds upon the central insight of previous designs [14,18,20,22,26,27,34,45,46] that coherence traffic can help us track inter-thread dependences, our final design is optimized for the requirements of lifeguards, as described later in this paper, including the need to handle logical races. Our solution to the logical race problem uses a mechanism similar to one used in Capo [23] for a completely different purpose (i.e., avoiding monitoring during system calls).…”

Section: Related Workmentioning

confidence: 99%

ParaLog

Vlachos¹,

Goodstein²,

Kozuch³

et al. 2010

Proceedings of the Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems

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Instruction-grain lifeguards monitor the events of a running application at the level of individual instructions in order to identify and help mitigate application bugs and security exploits. Because such lifeguards impose a 10-100X slowdown on existing platforms, previous studies have proposed hardware designs to accelerate lifeguard processing. However, these accelerators are either tailored to a specific class of lifeguards or suitable only for monitoring singlethreaded programs.We present ParaLog, the first design of a system enabling fast online parallel monitoring of multithreaded parallel applications. ParaLog supports a broad class of software-defined lifeguards. We show how three existing accelerators can be enhanced to support online multithreaded monitoring, dramatically reducing lifeguard overheads. We identify and solve several challenges in monitoring parallel applications and/or parallelizing these accelerators, including (i) enforcing inter-thread data dependences, (ii) dealing with inter-thread effects that are not reflected in coherence traffic, (iii) dealing with unmonitored operating system activity, and (iv) ensuring lifeguards can access shared metadata with negligible synchronization overheads. We present our system design for both Sequentially Consistent and Total Store Ordering processors. We implement and evaluate our design on a 16 core simulated CMP, using benchmarks from SPLASH-2 and PARSEC and two lifeguards: a data-flow tracking lifeguard and a memory-access checker lifeguard. Our results show that (i) our parallel accelerators improve performance by 2-9X and 1.13-3.4X for our two lifeguards, respectively, (ii) we are 5-126X faster than the time-slicing approach required by existing techniques, and (iii) our average overheads for applications with eight threads are 51% and 28% for the two lifeguards, respectively.

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“…But software memory race recording [7][8][9] can bring tremendous performance overhead for system, and software approach to support memory race recording also is difficult to realize. Therefore, many researchers have proposed cheap hardware memory race recorder to support multithreaded deterministic replay more efficiently in the architecture level recently, in particular [10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…Rerun [14] and Ref. [15] both use chunk-based logging approach to log memory races (episodes are like chunks in Rerun). Rerun achieves a log size on par with RTR with only a small fraction of hardware cost.…”

Section: Introductionmentioning

confidence: 99%