architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute

Li, He; Davis, James J.; Wickerson, John; Constantinides, George A.

doi:10.1109/tvlsi.2019.2945257

Cited by 11 publications

(5 citation statements)

References 25 publications

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“…A key point to notice in Theorems 2 and 3 is that they are concerned only with the existence of an iterate sequence with stable MSDs, and do not comment on how such a sequence can be constructed. The construction of the sequence with stable MSDs will still be application/algorithm-specific, with the designer needing to ensure that the computations performed in the fixed-point iteration will preserve the MSD stability as they are performed, such as through the use of online arithmetic or the ARCHITECT system [1].…”

Section: Msd Stability In Iterative Methodsmentioning

confidence: 99%

“…The redundant number system plays a key role in computer arithmetic, with uses ranging from carry-free addition, multiplication and division algorithms [3] to Most-significant Digit (MSD) first operations such as Online arithmetic [4] or the E-method for evaluating polynomials [5]. Recent work has extended MSD first arithmetic to the implementation of iterative methods, with the ARCHITECT framework proposed by Li et al in [1] showing large speed-ups in FPGA implementations of the Jacobi method by exploiting the ideas of "don't-change" stable MSDs and "don't-care" Least-significant Digits (LSDs) to reduce the number of total digits computed in each iteration. Prior work to analyze and exploit the stable MSDs, which are the MSDs that don't change their digit value in any future iteration, has been algorithm-specific, with works such as [2] and [5] starting with a specific algorithm and then showing that its iterate sequence has MSD stability.…”

Section: Introductionmentioning

confidence: 99%

“…We start by showing that a Fejér monotone sequence can have stable MSDs when represented using redundant numbers, and we then use that result to show that any iterative method whose iterates are a Fejér monotone sequence (such as fixed-point iterations of contractive Lipschitz continuous functions) can have digit stability. This allows us to derive theoretical guarantees for the existence of stable MSDs in the iterate sequence of both the Jacobi method (which was previously analyzed in [2]), and Newton's method (which was only experimentally shown to have stable digits in [1]) II. BACKGROUND…”

Section: Introductionmentioning

confidence: 99%

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Conditions for Digit Stability in Iterative Methods Using the Redundant Number Representation

McInerney¹

2022

Preprint

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Iterative methods play an important role in science and engineering applications, with uses ranging from linear system solvers in finite element methods to optimization solvers in model predictive control. Recently, a new computational strategy for iterative methods called ARCHITECT was proposed by Li et al. in [1] that uses the redundant number representation to create "stable digits" in the Most-significant Digits (MSDs) of an iterate, allowing the future iterations to assume the stable MSDs have not changed their value, eliminating the need to recompute them. In this work, we present a theoretical analysis of how these "stable digits" arise in iterative methods by showing that a Fejér monotone sequence in the redundant number representation can develop stable MSDs in the elements of the sequence as the sequence grows in length. This property of Fejér monotone sequences allows us to expand the class of iterative methods known to have MSD stability when using the redundant number representation to include any fixed-point iteration of a contractive Lipschitz continuous function. We then show that this allows for the theoretical guarantee of digit stability not just in the Jacobi method that was previously analyzed by Li et al. in [2], but also in other commonly used methods such as Newton's method.

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Section: Msd Stability In Iterative Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Conditions for Digit Stability in Iterative Methods Using the Redundant Number Representation

McInerney¹

2022

Preprint

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“…Online adders are special adder architectures which employ redundancy in data representation, allowing less-significant digits to correct errors introduced in those of higher signif- icance, and functioning in MSD-first fashion [27], [28]. In these adders, each input bit x i corresponds to a pair of bits, x + i and x − i , selected such that 27]. This is why O ADDER8 (the 8-bit online adder) has 34 inputs (four 8-bit inputs, plus a 2-bit carry-in) and 18 outputs (two 8-bit outputs, and a 2-bit carry-out).…”

Section: Online Addersmentioning

confidence: 99%

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Scarabottolo

Ansaloni

Constantinides

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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Approximate Logic Synthesis techniques have become popular in error-resilient systems, where accuracy requirements can be traded for improved energy efficiency. Many of these techniques operate on a circuit by substituting or removing some of its portions under a predefined error constraint; however, research on systematic methods to determine the error induced by such transformations is still at an early stage. We propose herein a generic framework for modeling maximum error in a circuit, called Partition and Propagate, which is a fundamental preliminary step for ALS. This framework is based on circuit partitioning and error propagation among the sub-circuits. We provide a sound, complete formal description of such framework, and we illustrate how two state-of-the-art algorithms can be subsumed by it. Moreover, we propose a novel gate-level errormodeling algorithm which is able to identify the whole range of possible errors induced by a given approximate transformation. We compare the three strategies and illustrate the efficiency of the new error-propagation methodology, which is able to identify accurate error bounds and, hence, guide ALS techniques to more valuable solutions.

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“…Redundant algorithm-based carry-free addition has attracted numerous attention due to its enhanced performance as compared with other adders, including faster speed and fixed delay irrespective of adder depth 14,15 . Unlike traditional least-significant-bit-first (LSBF) addition methods, carry-free adders (CFAs) facilitate most-significant-bit-first (MSBF) computations, thereby enabling arithmetic operations of arbitrary precision 16 . However, the efficient way to construct binary logic-based CFAs remains underexplored due to the intricate representation of signed numbers and hardware implementation complexity, which have limited their widespread applications.…”

Section: Introductionmentioning

confidence: 99%

Carry-Free Adder in Redundant Number System: the First and Only Demonstration of Ternary Logic’s Superiority Over Binary Logic

Huang,

Zhao,

et al. 2024

Preprint

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Ternary logic has attracted significant attention due to its higher data density and balanced number representation. Even though tremendous endeavor has been devoted to developing ternary logic arithmetic circuits with compact structures, its industrial applications have stagnated for years due to the inferior energy efficiency compared to binary systems. In this work, we introduce various carry-free arithmetic circuit designs based on ternary logic and redundant number systems (RNS). For the first time, our proposed ternary arithmetic circuits outperform their binary counterparts with equivalent computation capabilities in energy efficiency across various data widths. Various arithmetic circuits including mixed adders, mixed subtractors, and signed adders were designed and implemented. Comprehensive simulations of the proposed 4/8/12/16/32-bit arithmetic circuits were performed using the SMIC180 process design kit (PDK), which demonstrated significant performance advances over the existing binary logic-based circuits. Specifically, our 8-bit carry-free mixed adders and subtractors show reductions in power consumption by 35.5% and 40.8% respectively, operating at 200 MHz. Furthermore, our carry-free signed adders exhibit superior speed and double the operational frequency (200 vs. 100 MHz). When benchmarked against the binary approaches at the binary frequency limit, our circuits reduce the power consumption by 10.22%. These results not only demonstrate the great potential of our approach in broader computational applications but also shed insights into the energy-efficient, high-speed arithmetic circuit design based on ternary logic.

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architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute

Cited by 11 publications

References 25 publications

Conditions for Digit Stability in Iterative Methods Using the Redundant Number Representation

Conditions for Digit Stability in Iterative Methods Using the Redundant Number Representation

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Carry-Free Adder in Redundant Number System: the First and Only Demonstration of Ternary Logic’s Superiority Over Binary Logic

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