Approximate On-The-Fly Coarse-Grained Reconfigurable Acceleration for General-Purpose Applications

Brandalero, Marcelo; Beck, Antonio Carlos Schneider; Carro, Luigi; Shafique, Muhammad

doi:10.1109/dac.2018.8465930

Cited by 7 publications

(5 citation statements)

References 17 publications

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“…We have assessed the collective performance metrics for different CGRA sizes, in both SISD and SIMD modes with 16-bit (subword of 8-bit) inputs. BioCare is evaluated against approximate 16-bit X-CGRA [11], GP-CGRA [9]. We analysed Add/Muls candidates in X-CGRA and GP-CGRA and selected those with lowest resource×error bias.…”

Section: Resultsmentioning

confidence: 99%

“…This highlights the demand for a generic approximate SIMD ALU, that can also be utilized in health-monitoring platforms. Moreover, while Add/Mul are frequent functions in bio-signal processing workloads, [9], [15], [18] and our evaluations show that long latency/high power of division, not only limit application speed, but also consumes considerable portion of ALU area/energy (Fig. 1b).…”

Section: Introductionmentioning

confidence: 89%

“…Approximate CGRAs/Bio-signal Processing: As mentioned, Multi-access Edge Computing, MEC, is the solution to energyefficient processing of bio-signals [3]. Works in this cuttingedge track are, however, limited to power-gating PEs (having separate inexact Add/Mul/Div) [9]- [11]. Targeting bio-signal approximation, XBioSiP [13] has applied LSB simplification on kernels of an ECG program, albeit all fixed to 16-bit precision.…”

Section: Related Workmentioning

confidence: 99%

“…Still, to enable a real-time processing in 24/7 portable gadgets, higher throughput should be achieved in stringent power-budget. To cope with such design constraints, several approximation techniques have emerged, however, they suffer from inevitable routing-power and die-area overhead, due to collecting accuracy-configurable Add/Mul/Div units, with an inter-or intra-PE heterogeneity [9]- [11]. Approximation potentials are even more pronounced in bio-signal analysis, as 1) processing stage dissipates up to 70% of total energy in wearable nodes [12].…”

Section: Introductionmentioning

confidence: 99%

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BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

Ebrahimi

Kumar

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Coarse Grained Reconfigurable Architectures (CGRAs) have proved to be viable platforms for health monitoring applications. Targeting energy-efficiency, state-of-the-art (SoA) CGRAs are augmented with approximation techniques, while still maintain acceptable accuracy at final Quality of Result (QoR). However, such CGRAs suffer from overheads of collecting separate Add/Mul/Div units. We propose BioCare as an area-and energy-efficient CGRA for health-monitoring edge devices, which exploits the synergistic effects of multiple approximations across HW/SW stack. BioCare offers different levels of energy-accuracy trade-off through the plasticity of its small PEs, each can support precision-adaptability with a Single Instruction, Multiple Data (SIMD) manner. BioCare demonstrates its superiority over SoAs, by achieving up to 32% and 67% area-and energy-savings, with 3.6× higher throughput. In addition to analysis on multiple kernels, evaluations on a multi-kernel ECG application shows that BioCare speed-ups the QRS detection latency by 61%, with 0% loss in accuracy. Our implementations will be available at

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 89%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

Ebrahimi

Kumar

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…However, the general architecture derived from the template has ALUs with full functionality (logic+shift+add). Among prior works that propose different precision levels among the functional units, TRANSPIRE [33] supports a combination of integer and floating-point functional units, while on-the-fly CGRA [6] incorporates heterogeneous compute units each with diverse levels of approximation.…”

Section: Related Workmentioning

confidence: 99%

REVAMP: a systematic framework for heterogeneous CGRA realization

Bandara

Wijerathne

Mitra

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Coarse-Grained Reconfigurable Architectures (CGRAs) provide an excellent balance between performance, energy efficiency, and flexibility. However, increasingly sophisticated applications, especially on the edge devices, demand even better energy efficiency for longer battery life.Most CGRAs adhere to a canonical structure where a homogeneous set of processing elements and memories communicate through a regular interconnect due to the simplicity of the design. Unfortunately, the homogeneity leads to substantial idle resources while mapping irregular applications and creates inefficiency. We plan to mitigate the inefficiency by systematically and judiciously introducing heterogeneity in CGRAs in tandem with appropriate compiler support.We propose REVAMP, an automated design space exploration framework that helps architects uncover and add pertinent heterogeneity to a diverse range of originally homogeneous CGRAs when fed with a suite of target applications. REVAMP explores a comprehensive set of optimizations encompassing compute, network, and memory heterogeneity, thereby converting a uniform CGRA into a more irregular architecture with improved energy efficiency. As CGRAs are inherently software scheduled, any micro-architectural optimizations need to be partnered with corresponding compiler support, which is challenging with heterogeneity. The REVAMP framework extends compiler support for efficient mapping of loop kernels on the derived heterogeneous CGRA architectures.We showcase REVAMP on three state-of-the-art homogeneous CGRAs, demonstrating how REVAMP derives a heterogeneous variant of each homogeneous architecture, with its corresponding compiler optimizations. Our results show that the derived heterogeneous architectures achieve up to 52.4% power reduction, 38.1% area reduction, and 36% average energy reduction over the corresponding homogeneous versions with minimal performance impact for the selected kernel suite.

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Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications

Chandaka

Balaji²

2022

J Electron Test

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Approximate On-The-Fly Coarse-Grained Reconfigurable Acceleration for General-Purpose Applications

Cited by 7 publications

References 17 publications

BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge

REVAMP: a systematic framework for heterogeneous CGRA realization

Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications

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