Approximate Arai DCT Architecture for HEVC

Renda, Giovanni; Masera, Maurizio; Martina, Maurizio; Masera, Guido

doi:10.1109/ngcas.2017.38

Cited by 7 publications

(4 citation statements)

References 11 publications

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“…The importance of DCT in terms of scalability and minimal distortion demonstrated by Cariccia et al [21] as well as Renda et al [22] is quite noticeable. Because of the ability of DCT algorithms to produce high throughput, low power dissipation, and reduced chip area with primary objective of security, they are more popular amongst the researchers.…”

Section: Vlsi Designmentioning

confidence: 98%

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Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Desai

Mali

2018

VLSI Design

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Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

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Section: Vlsi Designmentioning

confidence: 98%

“…Brief analysis of various techniques [31][32][33][34][35][36][37] to develop such systems is given in Table 2. The frequency domain techniques demonstrated in [32][33][34][35][36][37] as well as [21,22] show better performance in terms of imperceptibility, capacity, robustness, and process.…”

Section: Vlsi Designmentioning

confidence: 99%

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Desai

Mali

2018

VLSI Design

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“…However, the rough approximation of the 8-point core and using it for larger sizes introduce more than 5% coding loss in terms of rate distortion performance (BD-BR). Renda et al [35] proposed to approximate the 8-point DCT-II transform by an exact low-complexity factorization of the 8-point DCT-II [42] to be used as core module in the generalized algorithm proposed in [34]. The 8×8 matrix multiplication is reduced to only 5 multiplications and 29 additions.…”

Section: A Multiple Transform Selection In Vvcmentioning

confidence: 99%

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Kammoun

Hamidouche

Philippe

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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The future video coding standard named Versatile Video Coding (VVC) is expected by the end of 2020. VVC will enable better coding efficiency than the current High Efficiency Video Coding (HEVC) standard. This coding gain is brought by several coding tools. The Multiple Transform Selection (MTS) is one of the key coding tools that have been introduced in VVC. The MTS concept relies on three transform types including Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII and DCT-VIII. Unlike the DCT-II that has fast computing algorithms, the DST-VII and DCT-VIII rely on more complex matrix multiplication. In this paper an approximation approach is proposed to reduce the computational cost of the DST-VII and DCT-VIII. The approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variant of DCT-II family mainly DCT-II and its inverse. Genetic algorithm is used to derive the optimal coefficients of the adjustment matrices. Moreover, an efficient hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform as it is the main core for DST-VII and DCT-VIII computations. The proposed 32-point 1D architecture including low cost adjustment stages allows the processing of a video in 2K and 4K resolutions at 1095 and 273 frames per second, respectively. A unified 2D implementation of forwardinverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain a video in 2K and 4K resolutions at 386 and 96 frames per second, respectively, while using only 12% of Alms, 22% of registers and 30% of DSP blocks of the Arria10 SoC platform.

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“…Additionally to the coefficients rounding approximation, also similarities between DCT matrices or decomposed (odd-even decomposition) DCT matrices blocks are exploited to reuse parts of the design for smaller or bigger block size transformations [27]. Decomposed DCT matrices blocks approximation to the same block has been also coupled to approximate computing at the data level: truncation of the matrix block coefficients in an odd-even decomposed matrix where odd block is used for both odd and even part has been proposed in literature [50]. In other cases, always relying on DCT matrix decomposition, block matrix coefficient simplification has not been driven by mathematical (simply rounding), input data (correlation between pixels) or data precision (truncation) motivations, but it has been driven by hardware implementation.…”

Section: Computation Level Approximationmentioning

confidence: 99%

Reconfigurable and approximate computing for video coding

Palumbo

2019

VLSI Architectures for Future Video Coding

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Systems perception capabilities are fundamental to make modern interconnected systems smart and, in this context, video coding is certainly a key technology. Video coding standards have been traditionally based on monolithic specifications coupled to a fixed set of profiles, capable of implementing different sub-set of functionalities of the given reference standard. Standards and profiles typically offer different features and enable different trade-offs that make them suitable for different applications and scenarios. Nevertheless, keeping the pace with constantly evolving scenarios and user's needs, for example in terms of offered quality or consumed power, is not that simple, and has led to continuous releases/updates of standards and profiles.Ideally designers should be allowed, at design-time, to select and combine coding tools and profiles to optimally match the given requirements, while guaranteeing that customized applications are still interoperable. Nevertheless, monolithic specifications tend to hide parallelism and the dataflow nature of video coding algorithms that, on the contrary, can be successfully exploited to guarantee efficient implementations and to play with different trade-offs [8].To address these issues, related to codecs design and customization, designers have been called to conceive efficient design-time methodologies

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Approximate Arai DCT Architecture for HEVC

Cited by 7 publications

References 11 publications

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Reconfigurable and approximate computing for video coding

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