Approximate Analysis of General Queuing Networks

Chandy, K. Mani; Herzog, Ulrich; Woo, L. S.

doi:10.1147/rd.191.0043

Cited by 210 publications

(39 citation statements)

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“…The approach that we take is a throughput-based method, similar in spirit to the Flow Equivalent Server (FES) model [11]. The main points of this method are recursive decomposition and aggregation.…”

Section: Overview Of the Modelmentioning

confidence: 99%

“…per-page time = serial groups DRAM latency + logical blocks per page BP C mfu/memory (11) For a thread that iterates over a large range, Execution time = pages × per_iteration time (12) where per_iteration time is typically a sum of per-page time calculated with every AMO group within the loop body, plus non-AMO code between the AMO groups. For example, the per_iteration time of the algorithm in Fig. 14 is a sum of execution time of the four steps.…”

Section: Estimating Total Execution Timementioning

confidence: 99%

“…effective_FUs = 3.0 (8) BPC mfu = 0.2500 (1) η = 0.5904 (5) effective_channels = 4.0 (9) BPC memory = 0.0472 (7) Because BPC memory < BPC mfu , memory bandwidth is the bottleneck. Apply BPC memory to (11) and we get TIME AMO1 = 2910 cycles per page Step 2) AMO2 through AMO6: Using a P unmask = 5% for both the MFU and memory, we have effective_FUs = 0.15 (8) η = 0.5375 (5) effective_channels = 4.0 (9) BPC memory = 0.0086 (7) effective_FUs < 1.0 and effective_channels > 1.0 ⇒ TIME AMOs 2 to 6 = 944 cycles per page (11) Step 3) the bit operations: Insert a 400-cycle delay for this non-AMO code block. This can be derived from existing analytical models [3,48].…”

Section: Using the Analytical Model: An Examplementioning

confidence: 99%

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Active memory controller

et al. 2012

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Inability to hide main memory latency has been increasingly limiting the performance of modern processors. The problem is worse in large-scale shared memory systems, where remote memory latencies are hundreds, and soon thousands, of processor cycles. To mitigate this problem, we propose an intelligent memory and cache coherence controller (AMC) that can execute Active Memory Operations (AMOs). AMOs are select operations sent to and executed on the home memory controller of data. AMOs can eliminate a significant number of coherence messages, minimize intranode and internode memory traffic, and create opportunities for parallelism. Our implementation of AMOs is cache-coherent and requires no changes to the processor core or DRAM chips.The work was done when most of the authors were at the University of Utah. The views and conclusions contained herein are those of the authors and should not be interpreted as representing those, either express or implied, of Intel, CAS, IBM, Chalmers, AMD, nVidia, or the University of Utah. In this paper, we present the microarchitecture design of AMC, and the programming model of AMOs. We compare AMOs' performance to that of several other memory architectures on a variety of scientific and commercial benchmarks. Through simulation, we show that AMOs offer dramatic performance improvements for an important set of data-intensive operations, e.g., up to 50× faster barriers, 12× faster spinlocks, 8.5×-15× faster stream/array operations, and 3× faster database queries. We also present an analytical model that can predict the performance benefits of using AMOs with decent accuracy. The silicon cost required to support AMOs is less than 1% of the die area of a typical high performance processor, based on a standard cell implementation.

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Section: Overview Of the Modelmentioning

confidence: 99%

Section: Estimating Total Execution Timementioning

confidence: 99%

Section: Using the Analytical Model: An Examplementioning

confidence: 99%

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Active memory controller

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“…Jackson [7] first showed that the equilibrium probability distribution P(S) of the state S of a network of first-comefirst-served queues is in the form of a product of terms that correspond to the state probabilities of the individual queues considered in isolation. Presently, most known networks with an exact solution for P(S) belong to the class of BCMP networks discovered and characterized by Baskett, Chandy, Muntz, and Palacios [1, 3,11]. Four types of service centers as well as open and closed routing chains are allowed.…”

Section: Introductionmentioning

confidence: 99%

“…In such a network the population vector N changes as a result of external arrivals into the network or customer departures from the network. We have shown that class local balance [1,3] implies chain local balance. Furthermore, routing chains possess the M =* M property [11].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Scaling and Growth Behavior of Queuing Network Normalization Constants

Lam

1982

J. ACM

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ABSTRACT. A sample dynamic scaling technique is shown that avoids both the overflow and underflow problems that are often encountered in the evaluation of normalization constants of closed product-form queuing networks W~th dynamic scaling, normalization constants for very large routing chain population sizes can be evaluated within the bounds of a relauvely small range of numbers. It is shown that the product-form solution possesses a local balance property and the M ~, M property with respect to routing chains. The relationships between normahzaUon constants of closed networks and certain equilibrium aggregate state probabdities in networks that permit external arrivals and departures are examined. The growth behavior of normalization constants is shown to be modeled by a birth-death process traversing over the set of chain population vectors

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Queueing Networks

and¹,

Boudriga²

2010

Fundamentals of Performance Evaluation of Computer and Telecommunication Systems

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Approximate Analysis of General Queuing Networks

Cited by 210 publications

References 4 publications

Active memory controller

Active memory controller

Dynamic Scaling and Growth Behavior of Queuing Network Normalization Constants

Queueing Networks

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