Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency

Venkatagiri, Radha; Mahmoud, Abdulrahman; Hari, Siva Kumar Sastry; Adve, Sarita V.

doi:10.1109/micro.2016.7783745

Cited by 45 publications

(43 citation statements)

References 33 publications

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“…As oppose to semi or non-automated mechanisms, SAGE [Samadi et al 2013] proposes an automated approach by using online monitoring mechanism designed for GPU kernels. Closest to our work, Approxilyzer [Venkatagiri et al 2016] tries to find noise tolerant instructions in an application and classifies them as Masked, SDC-Good/Maybe/Bad, and detectable errors. This approach is automated; however, it is only limited to single bit errors.…”

Section: Related Workmentioning

confidence: 99%

Toward Dynamic Precision Scaling

2018

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Based on the observation that application phases exhibit varying degrees of sensitivity to noise (i.e., accuracy loss) in computation during execution, this paper explores how Dynamic Precision Scaling (DPS) can maximize power efficiency by tailoring the precision of computation adaptively to temporal changes in algorithmic noise tolerance. DPS can decrease the arithmetic precision of noise-tolerant phases to result in power savings at the same operating speed (or faster execution within the same power budget), while keeping the overall loss in accuracy due to precision reduction bounded.

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Section: Related Workmentioning

confidence: 99%

Toward Dynamic Precision Scaling

2018

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“…Other techniques include selective n-modular redundancy in which a developer either manually or with the support of a dynamic fault-injection tool identifies instructions or regions of code that do not need to be protected for the application to produce an acceptable resultÐas determined by an empirical evaluation [Carbin and Rinard 2010;Thomas and Pattabiraman 2016;Venkatagiri et al 2016;Vishal Chandra Sharma 2016]. Another class of techniques is fault-tolerant algorithms that through the addition of algorithm-specific checking and correction code are tolerant to faults [Du et al 2012;Hoemmen and Heroux 2011;Sao et al 2016;Sao and Vuduc 2013].…”

Section: Application-specific Fault Tolerancementioning

confidence: 99%

Leto: verifying application-specific hardware fault tolerance with programmable execution models

Boston

Gong

Carbin

2018

Proc. ACM Program. Lang.

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Researchers have recently designed a number of application-specific fault tolerance mechanisms that enable applications to either be naturally resilient to errors or include additional detection and correction steps that can bring the overall execution of an application back into an envelope for which an acceptable execution is eventually guaranteed. A major challenge to building an application that leverages these mechanisms, however, is to verify that the implementation satisfies the basic invariants that these mechanisms requireÐgiven a model of how faults may manifest during the application's execution. To this end we present Leto, an SMT-based automatic verification system that enables developers to verify their applications with respect to an execution model specification. Namely, Leto enables software and platform developers to programmatically specify the execution semantics of the underlying hardware system as well as verify assertions about the behavior of the application's resulting execution. In this paper, we present the Leto programming language and its corresponding verification system. We also demonstrate Leto on several applications that leverage application-specific fault tolerance mechanisms.

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“…This makes it infeasible to conduct exhaustive fault injection campaigns for workloads with a high number of dynamic instructions. This is why prior work has either randomly sampled the error space, or used error clustering to find classes of equivalent errors which could then be pruned to facilitate exhaustive fault injection campaigns [14], [15], [16]. However, all of these papers have focused on single-bit errors, and hence their heuristics for sampling and clustering are specific to the single bit-flip scenario.…”

Section: Error Clustering and Error Samplingmentioning

confidence: 99%

“…Further, almost all the existing techniques for pruning the error space [14], [15], [16] work with the single-bit fault model, and are not easily extensible to multiple-bit errors. Therefore, in this paper, we also propose three ways of pruning the error space based on the fault injection results obtained.…”

Section: Introductionmentioning

confidence: 99%

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One Bit is (Not) Enough: An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors

Sangchoolie¹,

Pattabiraman

Karlsson

2017

2017 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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Abstract-Recent studies have shown that technology and voltage scaling are expected to increase the likelihood that particle-induced soft errors manifest as multiple-bit errors. This raises concerns about the validity of using single bit-flips for assessing the impact of soft errors in fault injection experiments. The goal of this paper is to investigate whether multiple-bit errors could cause a higher percentage of silent data corruptions (SDCs) compared to single-bit errors. Based on 2700 fault injection campaigns with 15 benchmark programs, featuring a total of 27 million experiments, our results show that single-bit errors in most cases yields a higher percentage of SDCs compared to multiple-bit errors. However, in 8% of the campaigns we observed a higher percentage of SDCs for multiple-bit errors. For most of these campaigns, the highest percentage of SDCs was obtained by flipping at most 3 bits. Moreover, we propose three ways of pruning the error space based on the results.

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Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency

Cited by 45 publications

References 33 publications

Toward Dynamic Precision Scaling

Toward Dynamic Precision Scaling

Leto: verifying application-specific hardware fault tolerance with programmable execution models

One Bit is (Not) Enough: An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors

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