APPROX-NoC

Abstract

The trend of unsustainable power consumption and large memory bandwidth demands in massively parallel multicore systems, with the advent of the big data era, has brought upon the onset of alternate computation paradigms utilizing heterogeneity, specialization, processor-in-memory and approximation. Approximate Computing is being touted as a viable solution for high performance computation by relaxing the accuracy constraints of applications. This trend has been accentuated by emerging data intensive applications in domains like image/video processing, machine learning and big data analytics that allow inaccurate outputs within an acceptable variance. Leveraging relaxed accuracy for high throughput in Networks-on-Chip (NoCs), which have rapidly become the accepted method for connecting a large number of on-chip components, has not yet been explored. We propose APPROX-NoC, a hardware data approximation framework with an online data error control mechanism for high performance NoCs. APPROX-NoC facilitates approximate matching of data patterns, within a controllable value range, to compress them thereby reducing the volume of data movement across the chip. Our evaluation shows that APPROX-NoC achieves on average up to 9% latency reduction and 60% throughput improvement compared with state-of-the-art NoC data compression mechanisms, while maintaining low application error. Additionally, with a data intensive graph processing application we achieve a 36.7% latency reduction compared to state-of-the-art compression mechanisms.

HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models

“…Approximate storage is often for larger capacity for high-density image storage [27][28][29][30]. 3 [31] and network on chip architectures [32][33][34][35][36] are proposed for higher network throughput using the critical feature of data type information or dual scaling voltage.…”

“…This approximate computing paradigm can be applied in different components of application-specified accelerators with different quality-power (or performance) tradeoffs at different abstractions layers [2]. There have been a variety of approximate techniques proposed for gaining power saving or performance improvement, which cover all the sites in approximate computing [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], approximate storage [18][19][20][21][22][23][24][25][26][27][28][29][30], and approximate communication [31][32][33][34][35][36]. How to utilize these approximate techniques is a significant issue for designing a cost-effective approximate accelerator.…”

“…It calculates the output quality of approximate configuration with a few formulas very quickly. However, these analytical models are usually limited to certain approximate sites such as approximate adders or approximate multipliers for calculation [40,41], approximate SRAM/DRAM/SSD/PCM [42][43][44][45] for storage, and approximate data transmission for communication [31][32][33][34][35][36]. Particularly, there are a variety of accuracy-power/performance tradeoffs for a specified approximate component.…”

Approximate nanophotonic interconnects

“…It also contributes to improve power consumption of memories [12] and sensors for IoT applications [14]. In the context of electrical NoCs, approximation techniques have been deployed to reduce the number of transmitted bits [3]. In [1], voltage lowering techniques are applied to lower the robustness of links transmitting the least significant bits of FP numbers.…”