Approach to Find Shortest Path Using Ant Colony Algorithm

Basha, Mudasar; Kumar, Mahendra; Pranav, Vemulapalli Sai; Rehman, Bilawal

doi:10.1007/978-981-10-5903-2_130

Cited by 3 publications

(2 citation statements)

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“…The problem of deterministically creating a test example for a deficit (Sa {0,1}) is to detect the assignment of a combination of logical values (0 or 1) to the main inputs that recreate the deficiency (line support) and to monitor the deficiency [24][25][26][27][28].…”

Section: B Problem Modelmentioning

confidence: 99%

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Logical Fault Modelling Algorithm for Stuck-at-fault

Priyadarshini*,

Agarwal,

Ravindran

et al. 2020

IJRTE

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With miniaturization happening around with the technology, it’s very important that the faults associated with these circuitsto get accurate results, especially electronics circuits. Besides, finding these faults is a tough job as there will be several test inputs that needs to be tested to check the circuit is fault free or not. Stuck at line is a deficiency prototype used as a part of computerized testing circuit. When any of the line in the circuit is stuck permanently at power supply or ground giving unwanted output, this is called fault. This paper describes about a technique that can be used to find stuck at fault and display the test vectors that generates the faulty output.Any self-assertive different shortcoming in combinational and consecutive circuits can be mimicked and tried utilizing the displayed stuck at fault model. High fault coverage is especially significant during assembling test, and strategies. Stuck at fault results are presented and detected. The outcomes of single stuck at faults are presented in this paper using Verilog code.

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Section: B Problem Modelmentioning

confidence: 99%

“…These models mimic the physical defect behavior while facilitating the test generation process. Logical faults can be designed as structural and functional faults [28][29][30][31][32].…”

Section: Types Of Faultsmentioning

confidence: 99%