Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs

Santos, André Flores dos; Tambara, Lucas Antunes; Benevenuti, Fabio; Tonfat, Jorge; Kastensmidt, Fernanda Lima

doi:10.1007/978-3-319-56258-2_18

Cited by 7 publications

(7 citation statements)

References 4 publications

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“…The failed modules can be recovered using DPR. In [7], it was proven that 6MR was more reliable than 5MR, with λs (SEU rate) 10 times higher than λ d (DEU rate) based on the data in [3,15]. The reliability was calculated by simulating Markov models for 5MR and 6MR using SHARPE [16].…”

Section: Methodsmentioning

confidence: 99%

“…Failures and repair times are both assumed to be exponentially distributed; hence, the repair rate µ and the failure rate λ are constant [10]. In [7], it was proven that 6MR was more reliable than 5MR, with λs (SEU rate) 10 times higher than λd (DEU rate) based on the data in [3,15]. The reliability was calculated by simulating Markov models for 5MR and 6MR using SHARPE [16].…”

Section: Effect Of Failure Rates Ratio On Reliabilitymentioning

confidence: 99%

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FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

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Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

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Section: Methodsmentioning

confidence: 99%

Section: Effect Of Failure Rates Ratio On Reliabilitymentioning

confidence: 99%

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

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“…Thanks to the evolution of HLS tools, the precise modeling of the underlying hardware has been facilitated, which provides an opportunity to perform such studies comprehensively with an accuracy close to the real hardware. This approach is also followed by some recent works to study the resilience of several other applications [8], [9], [10], [11].…”

Section: A Different Methodologies To Study Nn Resiliencementioning

confidence: 99%

“…This approach can lead to a decreased development time with an early evaluation of the final design, while conforming to final power, energy, performance, and resilience goals in comparison to the in-silicon ASIC/FPGA implementation. For instance, an HLS-based approach has been used in recent research to study the resilience of accelerators [8], [9], [10], [11]. In this paper, we also use an HLS-based approach to study accelerator resilience.…”

Section: Introductionmentioning

confidence: 99%

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

Salami

Ünsal

Kestelman

2018

2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute-and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular fault characterization and mitigation. By following a High Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.

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“…By contrast, our work focuses on minimizing the resources needed for TMR and can intentionally neglect self-containment of SEUs within a TMR module for additional resource savings. Dos Santos et al [22] investigated another TMR-based HLS design flow on SRAMbased FPGAs and compares the reliability of these designs with their respective unhardened equivalents. Compared to our work, our heuristic focuses on making tradeoffs between redundancy and area, which can include full TMR.…”

Section: Related Workmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs

Cited by 7 publications

References 4 publications

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

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