Applying the zeros switch-off technique to reduce static energy in data caches

Ubal, Rafael; Sahuquillo, Julio; Petit, Salvador; López, Pedro

doi:10.1109/sbac-pad.2006.8

Cited by 2 publications

(5 citation statements)

References 19 publications

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“…We find that most applications exhibit regular flip and duty cycle patterns, although they are not always uniformly distributed, which exacerbates the HCI and BTI effects on a small number of cells within the 512-bit cache lines. Results also confirm previous work [9], [10] claiming that most applications write a significant number of near-zero and zero data values into the cache. This behavior has been exploited in the past to address static energy consumption [9] and performance with data compression [10].…”

Section: Introductionsupporting

confidence: 89%

“…Results also confirm previous work [9], [10] claiming that most applications write a significant number of near-zero and zero data values into the cache. This behavior has been exploited in the past to address static energy consumption [9] and performance with data compression [10]. Unlike these works, this paper takes advantage of such a behavior to mitigate aging.…”

Section: Introductionsupporting

confidence: 89%

“…For the proposed SZB mechanism, simple hardware is required to compute the C SZB bits and to forward zero bytes [9]. Figures 7(a) and 7(b) show the required circuitry for a cache word.…”

Section: Hardware Implementation and Operationmentioning

confidence: 99%

“…Otherwise, the cells are powered on to store the fetched data. Finally, notice that the simple SZB circuitry consisting of control bits, sleep transistors, and remaining read/write hardware has a low area overhead (11.76% of the 16KB L1 cache) [9].…”

Section: Cszb2 Cszb1 Cszb0mentioning

confidence: 99%

“…The delay of each 4-to-1 multiplexer used to implement the shift functions is 0.088ns, whereas muxing the control bits adds a delay of 0.044ns. The delay of the SZB OR gates and tristate buffers can be assumed to be negligible [9].…”

Section: ) Timingmentioning

confidence: 99%

See 4 more Smart Citations

On Microarchitectural Mechanisms for Cache Wearout Reduction

Valero

Miralaei

Petit

et al. 2017

IEEE Trans. VLSI Syst.

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Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic '0' to '1' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especially acute in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical for performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon previous studies showing that logic '0' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this work introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic '0' values are stored in the cells by switching off specific data bytes. Experimental results show that the threshold voltage degradation savings range from 21.8% to 44.3% depending on the application.

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Section: Introductionsupporting

confidence: 89%

Section: Introductionsupporting

confidence: 89%

“…For the proposed SZB mechanism, simple hardware is required to compute the C SZB bits and to forward zero bytes [9]. Figures 7(a) and 7(b) show the required circuitry for a cache word.…”

Section: Hardware Implementation and Operationmentioning

confidence: 99%

Section: Cszb2 Cszb1 Cszb0mentioning

confidence: 99%

Section: ) Timingmentioning

confidence: 99%

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On Microarchitectural Mechanisms for Cache Wearout Reduction

Valero

Miralaei

Petit

et al. 2017

IEEE Trans. VLSI Syst.

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A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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Abstract-The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

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Applying the zeros switch-off technique to reduce static energy in data caches

Abstract: Abstract

Cited by 2 publications

References 19 publications

On Microarchitectural Mechanisms for Cache Wearout Reduction

On Microarchitectural Mechanisms for Cache Wearout Reduction

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

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