Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures

Abstract

We propose a novel technique for reducing the power consumed by the on-chip cache on SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay(ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory subsystem power consumption and 47% savings in energydelay product (ED).

Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems

“…© Elsevier collecting the overall accesses count to each LLC bank by each core. The trace strategy requires instrumenting and running the application under representative conditions or to simulate its execution in a cycle-accurate, maybe a fullsystem, simulator implementing all the details of the system memory hierarchy [41], [39], [55]. The bank_count approach delivers coarser information than trace-based strategies but can be adopted more easily by adding only specific hardware counters to measure the number of accesses to the LLC banks from each core [44].…”

“…taking them from the executable binary, or calculating them at runtime after a phase where the running application is profiled. To activate the optimized memory layout, the OS fills a small hardware remap table in each core, similarly to some existing approaches [41], [42], [43]. Specifically, the remap table is accessed from a core before the LLC access (e.g.…”

“…They try to leave some slices without accesses so that they can be switched off to save energy. To populate the table, in [41] they utilize offline genetic algorithms based on application profiling, while in [43] they propose a runtime technique that estimates the working set size and the consequent cache space need.…”