Applying an XC6200 to real-time image processing

Woods, Roger; Trainor, David; Heron, J.

doi:10.1109/54.655180

Cited by 25 publications

(12 citation statements)

References 7 publications

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“…Our previous work [3,4] corroborates this conclusion and shows that it is beneficial to maintain a data flow approach at the register transfer level. Success and significant speed increases over sequential architectures have also been shown in the literature for low-level mappings that use this approach [5][6][7].…”

Section: B the Mapping Processmentioning

confidence: 87%

Design Patterns for Image Processing Algorithm Development on FPGAs

Gribbon

Bailey

Johnston

2005

TENCON 2005 - 2005 IEEE Region 10 Conference

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FPGAs are often used as implementation platforms for real-time image processing applications because their structure allows them to exploit spatial and temporal parallelism. Such parallelization is subject to the processing mode and hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the software algorithm in the process of mapping it to hardware. To aid in the process this paper proposes the application of design patterns which embody experience and through reuse provide tools for solving particular mapping problems. Issues involved in applying design patterns in this manner are outlined and discussed.

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Section: B the Mapping Processmentioning

confidence: 87%

Design Patterns for Image Processing Algorithm Development on FPGAs

Gribbon

Bailey

Johnston

2005

TENCON 2005 - 2005 IEEE Region 10 Conference

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“…Implementations using distributed arithmetic (DA) reduce the number of multiplications required, but still result in relatively large, low latency hardware. Woods et al [3] used a combination of 1D DCTs, distributed arithmetic, and transpose buffers on a Xilinx XC6264 to generate such a design that utilized 30 percent of total chip area. Bukhari et al [4] investigated the implementation of a modified Loeffler algorithm for 8x8 DCTs on various FPGAs.…”

Section: Fpgasmentioning

confidence: 99%

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Braganza

Leeser

2008

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

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Phase unwrapping is the process of converting discontinuous phase data into a continuous image. This procedure is required by any imaging technology that uses phase data such as MRI, SAR or OQM microscopy. Such algorithms often take a significant amount of time to process on a general purpose computer, rendering it difficult to process large quantities of information. This paper compares implementations of a specific phase unwrapping algorithm known as Minimum L P norm unwrapping on a Field Programmable Gate Array (FPGA) and on a Graphics Processing Unit (GPU) for the purpose of acceleration. The computation required involves a matrix preconditioner (based on a DCT transform) and a conjugate gradient calculation along with a few other matrix operations. These functions are partitioned to run on the host or the accelerator depending on the capabilities of the accelerator. The tradeoffs between the two platforms are analyzed and compared to a General Purpose Processor (GPP) in terms of performance, power and cost.

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“…This has included the reversing of broadcast lines and manipulating the cell functionality. Sout *-SinEEi(p.q)EBCin (10) Cout -Sin. Cin+Sin(p • q)+ Cin(p. q) (11) Sout-Ai(pBi)Ci To fully exploit partial reconfiguration, a more suitable full adder circuit for the XC6200 is possible.…”

Section: Dependence Graph Matchingmentioning

confidence: 99%

Accelerating run-time reconfiguration on custom computing machines

Heron

Woods

1998

SPIE Proceedings

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Custom computers comprising of a host processor and FPGAs have been proposed to accelerate computationally complex problems. Whilst the FPGA implementation might be considerably faster than its microprocessor counterpart, this performance acceleration can be degraded by the time to reconfigure the FPGA hardware. This paper demonstrates a technique for developing circuits that can reduce the reconfiguration overhead. Circuits for three basic arithmetic functions multiplication, division and square root have been developed using the Xilinx XC6200 reconfigurable FPGA family. Reconfiguration times have been measured by downloading the designs to the VCC HOTWorks custom computing board. A reduction in reconfiguration time of up to 75% has been demonstrated using this design approach.

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Applying an XC6200 to real-time image processing

Cited by 25 publications

References 7 publications

Design Patterns for Image Processing Algorithm Development on FPGAs

Design Patterns for Image Processing Algorithm Development on FPGAs

Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

Accelerating run-time reconfiguration on custom computing machines

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