Applying a submicron mismatch model to practical IC design

Guardiani, Carlo; Tomasini, A.; Benkoski, J.; Quarantelli, M.; Gubian, P.

doi:10.1109/cicc.1994.379715

Cited by 15 publications

(3 citation statements)

References 10 publications

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“…Although several corrections and extensions to the DSM region, such as those presented in [12], [15], and more recently in [19] and [16], have been proposed, the model proposed by Pelgrom et al [11] is still the most widely used in the current practice.…”

Section: A Mismatch Modelingmentioning

confidence: 99%

Analysis of the impact of process variations on clock skew

Zanella

Nardi

Neviani

et al. 2000

IEEE Trans. Semicond. Manufact.

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In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution networ

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Section: A Mismatch Modelingmentioning

confidence: 99%

Analysis of the impact of process variations on clock skew

Zanella

Nardi

Neviani

et al. 2000

IEEE Trans. Semicond. Manufact.

Self Cite

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“…As a main result, identically designed and biased devices display different statistical behaviors [1]. Since MOS transistor mismatch constitutes a serious limiting factor for the accuracy of VLSI circuits including digital-to-analog converters, sense amplifiers for memory arrays, reference sources, etc., accurate statistical modeling of transistors is a critical factor in designing ICs [2], [3]. Recent works have proposed, for short devices, changes in the local variation term of the well-known Pelgrom's mismatch model [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Layout-based statistical modeling for the prediction of the matching properties of MOS transistors

Conti

Crippa

Orcioni

et al. 2002

IEEE Trans. Circuits Syst. I

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A new methodology for statistical mismatch analysis of MOS transistor pairs is presented. Size and shape, as well as placement and partitioning of devices are taken into account by using a statistical approach based on stochastic process theory. The method depends on device geometry and mutual distances between devices and has been developed by first defining a transformation which maps the statistical behavior of the technological parameters considered as sources of errors into the behavior of device parameters. A useful expression for the parameter mismatch variance depending on the layout has been derived by assuming a particular form for the autocorrelation function of process parameters. Finally, the method has been used to analyze and compare the mismatch effect on several interdigitated and common-centroid structures.

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“…Additive error arises from threshold offsets between the pairs of input MOS in the squaring circuit. As these transistors are neighboring and non-minimum (5pmx3pm), we expect a matching in excess of 8 bits (< 8mV offset over a 2V dynamic) [17].…”

Section: 3: Precision Limitations Of Current-modementioning

confidence: 99%

Array-based analog computation: principles, advantages and limitations

Krämer

Proceedings of Fifth International Conference on Microelectronics for Neural Networks

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Analog implementations of Neural Networks and other computing architectures have gained increasing interest over the last decade.The field is at a critical juncture: continued interest will depend on the ability to demonstrate a clear advantage over digital solutions to problems of commercial interest. The Neural Network Design Group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and implementations of Neural Network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because oftheir efficiency and regularity, have formed the basis of most of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate Flash-EEPROM devices for both non-volatile analog storage and computation. This paper will share insights into the lessons we have learned, the results we have achieved, and the limitations we have encountered. Particular emphasis will be made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.

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Applying a submicron mismatch model to practical IC design

Cited by 15 publications

References 10 publications

Analysis of the impact of process variations on clock skew

Analysis of the impact of process variations on clock skew

Layout-based statistical modeling for the prediction of the matching properties of MOS transistors

Array-based analog computation: principles, advantages and limitations

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