Applied TCAD in Mega-Bits Memory Design

Abstract

This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based circuit model parameter generation for chip design purpose is one of the key topics in TCAD. Several critical phenomena, such as CMOS latchup etc., were also analyzed to verify feasibility and performance of the memory process. Two months of TCAD analysis were required, in which twelve sets of MOS model parameters were generated by VISTA with the computational cost of six hours on six CPUs of SGI-IRIS machines. Basic Data for TCAD DesignFor submicron devices, the shallow junction formation is one of the essential processes which determine the device performance. To verify the impurity profile of ion-implanted and annealed diffusion layer, we used SIMS measurement for B, P, and As impurities. Over a hundred samples with various doping conditions have been analyzed. Enhanced diffusion model parameters with annealing temperature and dose have been extracted. Figure 1 shows an example of a Phosphorous implantation/diffusion profile which exhibits dose dependent TED (Transient Enhanced Diffusion) phenomena [I]. The two-dimensional profile of the Phosphorous diffusion was also verified as shown in Fig. 2 [2]. The result shows an isotropic nature of TED for Phosphorous. In circuit design, threshold control and driving current of the device are two major characteristics which determine chip performance and yield. We found an anomalous degradation of submicron MOS driving current based on a study of intrinsic drain current, as shown in Fig. 3 [3]. A simple model which describes carrier-velocity-saturation has been developed to clarify the phenomena. Experimental Id, -L curves in submicron NMOS and the proposed model allow us prediction of effective drain current of submicron NMOS as shown in Fig. 4. Analysis of Critical PhenomenaIn CMOS memory process, a couple of critical phenomena have to be evaluated. Simulation works on CMOS latchup immunity [4], memory cell alpha-particle induced soft error [ 5 ] , Si crystal defects formation due to LOCOS process related mechanical stress [6] and electric-field enhanced SRH recombination [7] have been conducted.